Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper hand...
详细信息
ISBN:
(数字)9781510617247
ISBN:
(纸本)9781510617247;9781510617230
Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-mu m CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure.
A set of samples of glass fiber reinforced polymer composites with Teflon inclusions in the shape of pentagram have been specifically designed and fabricated for the purpose of assessing the efficacy and practicality ...
详细信息
A set of samples of glass fiber reinforced polymer composites with Teflon inclusions in the shape of pentagram have been specifically designed and fabricated for the purpose of assessing the efficacy and practicality of terahertz (THz) time domain spectroscopy (TDS) system in non-destructive evaluation (NDE), in side-by-side comparison with X-ray computed tomography (CT), and ultrasonic imaging. The samples feature systematic variation of Teflon inclusions of a variety of thicknesses and placement depths. An improved THz imaging algorithm is proposed and demonstrated to enhance the capability of THz-TDS detection by adding an appropriate window for sampling the reflected time-domain waveform a posteriori. Additionally, image fusion algorithm based on block segmentation is applied to combine multiple imaging detection results, leading to further improvement of the final defect detection capability. Comparative analysis of the detection results among THz-TDS, X-ray CT, and ultrasonic imaging is carefully carried out to assess the merits and disadvantages of each technique, and to attempt to find a proper place for THz-TDS imaging in the traditional arsenal of NDE tools.
imageprocessing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of s...
详细信息
imageprocessing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-basedimage operations is presented in this paper. The architecture is based on a 2D systolic array of 7 x 7 configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to 7 x 7, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of 3.16 GOPs at a 60 MHz clock frequency and a processing time of 8.35 milliseconds for 7 X 7 generic window-based operators on 512 x 512 gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.
暂无评论