A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning

作     者：Cho, SH Xanthopoulos, T Chandrakasan, AP 

作者机构：MIT Cambridge MA 02139 USA 

出 版 物：《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 (IEEE Trans Very Large Scale Integr VLSI Syst)

年 卷 期：1999年第7卷第2期

页      面：249-257页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Sharp Corporation 

主　　题：Huffman low power MPEG-2 table partitioning variable length decoder 

摘      要：Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLD s) are primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor, In this paper, a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce power. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 mu W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-mu m CMOS technology, More than an order of magnitude power reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT.