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An Efficient Design of variable length decoder for MPEG-1/2/4

IEEE TRANSACTIONS ON MULTIMEDIA 2008年第7期10卷 1307-1315页

作者： Chen, Pei-Yin Lin, Yi-Ming Cho, Min-Yi Natl Cheng Kung Univ Dept Comp Sci & Informat Engn Tainan 701 Taiwan

In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 mu m process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.

关键词： Area-efficient MPEG-1/2/4 variable length decoder

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A low-power VLSI implementation for variable length decoder in MPEG-1 layer III

A low-power VLSI implementation for variable length decoder ...

引用

Conference on Embedded Processors for Multimedia and Communications

作者： Tsai, TH Liu, CN Chen, WC Natl Cent Univ Dept Elect Engn Chungli 32054 Taiwan

ISBN: (纸本)0819452122

NPEG Layer III (MP3) audio coding algorithm is a widely used audio coding standard. It involves several complex coding techniques and is therefore difficult to create an efficient architecture design. The variable length decoding (VLD) e.g. Huffman decoding, is an important part of MP3. which needs great amount of search and memory access operations. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal statistics of variable length codes to reduce power and a two-level table lookup method is presented. The decoder was designed based on simplicity and low-cost, low power consumption while retaining the high efficiency requirements. The total power saving is about 67%.

关键词： MP3 low power audio variable length decoder VLSI

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A low-power variable length decoder for MPEG-2 based on successive decoding of short codewords

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 2003年第2期50卷 73-82页

作者： Lee, SW Park, IC Korea Adv Inst Sci & Technol Dept Elect Engn & Comp Sci Taejon 305701 South Korea

This paper presents a low-power variable length decoder exploiting the statistics of successive codewords. The decoder employs small look-up tables working as fixed caches to reduce the number of activations of a variable length code detector where considerable power is consumed. The power simulation results estimated using PowerMill show that 35% energy is reduced on the average compared to the previous low-power scheme.

关键词： Huffman low power MPEG-2 variable length code variable length decoder

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variable length decoder on dynamically reconfigurable cell array processor

Variable length decoder on dynamically reconfigurable cell a...

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Conference on Reconfigurable Technology - FPGAs and Reconfigurable Processors for Computing and Communications III

作者： Komoku, K Morishita, T Hatano, F Teramoto, I Okayama Prefectural Univ Fac Comp Sci & Syst Engn Soja Okayama 7191197 Japan

ISBN: (纸本)0819442496

Three kinds of basic variable length decoder were implemented on Dynamically Reconfigurable Cell Array Processor. Traditional method, Leading zeros method, Generated unique address method were discussed. The number of required resources for each decoder was described. Especially, in Generated unique address method, the variable length decoder circuit size on Dynamically Reconfigurable Cell Array Processor was quite small.

关键词： reconfigurable processor dynamically reconfigurable variable length decoder variable length Code MPEG

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A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1999年第2期7卷 249-257页

作者： Cho, SH Xanthopoulos, T Chandrakasan, AP MIT Cambridge MA 02139 USA

variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLD's) are primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor, In this paper, a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce power. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 mu W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-mu m CMOS technology, More than an order of magnitude power reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT.

关键词： Huffman low power MPEG-2 table partitioning variable length decoder

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High-performance variable length decoder with two-word bit stream segmentation

High-performance variable length decoder with two-word bit s...

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Conference on Digital Compression Technologies and Systems for Video Communications

作者： Bakhmutsky, M PHILIPS RES BRIARCLIFF MANORNY

ISBN: (纸本)0819423564

Implementing a high-performance variable length decoder (VLD) presents a major challenge in building an MPEG-2 compliant HDTV video decoder. The capability of the VLD to process macroblocks in real-time can save memory and simplify decoder architectures. For an MPEG-2 main profile, high level compliant HDTV video decoder, this means that the VLD must be able to decode macroblocks at rates exceeding 100 million code words per second. Partitioning the system on the VLD level increases decoder complexity and memory utilization. It is therefore desirable to conceive of a 'one-piece' VLD capable of performing the required operations economically and in real-time. The process of decoding entropy-encoded variable length bit streams is inherently serial in nature. In the VLD, the parallel processing of the bit stream located between the resynchronization points is therefore limited. A unique technique of high-speed parallel bit stream processing is described. This technique is based on a non-traditional two- word bit stream segmentation method optimized for high-speed word length decoding. Applied to the main body of the bit stream, it produces excellent performance results in both consumer and professional profiles of MPEG where decoder partitioning at the VLD level might otherwise be the norm.

关键词： variable length decoder video decoder VLD HDTV MPEG-2

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