Design of multiple-valued programmable logic array with unary function generators

作     者：Hata, Y Kamiura, N Yamato, K 

作者机构：Himeji Inst Technol Dept Comp Engn Himeji Hyogo 6712201 Japan Hyogo Univ Dept Econ & Informat Sci Kakogawa 6750101 Japan 

出 版 物：《IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS》 (电子信息通信学会汇刊：信息与系统)

年 卷 期：1999年第E82D卷第9期

页      面：1254-1260页

核心收录：

学科分类：0810[工学-信息与通信工程] 08[工学] 0835[工学-软件工程] 081001[工学-通信与信息系统] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：multiple-valued logic programmable logic array unary function logic design minimization 

摘      要：This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM-form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as ([log(2) p]-p upsilon + p(n - upsilon) + 1) p(n-1) to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.