A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

作     者：Legat, Uros Biasizzo, Anton Novak, Franc 

作者机构：Jozef Stefan Inst Ljubljana 1000 Slovenia 

出 版 物：《MICROPROCESSORS AND MICROSYSTEMS》 (微处理机与微型系统)

年 卷 期：2011年第35卷第4期

页      面：405-416页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Advanced Encryption Standard error-detection Built-in self-test FPGA fault modelling SEU mitigation 

摘      要：This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead. (C) 2011 Elsevier B.V. All rights reserved.