IATAC: A Smart Predictor to Turn-Off L2 Cache Lines

作     者：Abella, Jaume Gonzaález, Antonio Vera, Xavier 

作者机构：Computer Architecture Department Universitat Politècnica de Catalunya-Barcelona Jordi Girona 1-3 Barcelona 08034 Spain Intel Barcelona Research Center Intel Labs UPC Jordi Girona 29 Barcelona 08034 Spain Institute for Computing Systems Architecture School of Informatics University of Edinburgh Edinburgh United Kingdom 

出 版 物：《ACM Transactions on Architecture and Code Optimization》 (ACM Trans. Archit. Code Optim.)

年 卷 期：2005年第2卷第1期

页      面：55-77页

学科分类：0810[工学-信息与通信工程] 1205[管理学-图书情报与档案管理] 0808[工学-电气工程] 08[工学] 0835[工学-软件工程] 0811[工学-控制科学与工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Cache memories Design L2 cache Low power Performance Turning off cache lines 

摘      要：As technology evolves, power dissipation increases and cooling systems become more complex and expensive. There are two main sources of power dissipation in a processor: dynamic power and leakage. Dynamic power has been the most significant factor, but leakage will become increasingly significant in future. It is predicted that leakage will shortly be the most significant cost as it grows at about a 5× rate per generation. Thus, reducing leakage is essential for future processor design. Since large caches occupy most of the area, they are one of the leakiest structures in the chip and hence, a main source of energy consumption for future processors. This paper introduces IATAC (inter-access time per access count), a new hardware technique to reduce cache leakage for L2 caches. IATAC dynamically adapts the cache size to the program requirements turning off cache lines whose content is not likely to be reused. Our evaluation shows that this approach outperforms all previous state-of-the-art techniques. IATAC turns off 65% of the cache lines across different L2 cache configurations with a very small performance degradation of around 2%. © 2005, ACM. All rights reserved.