Compact Si JFET model for cryogenic temperature

作     者：Petrosyants, Konstantin O. Ismail-zade, Mamed R. Sambursky, Lev M. 

作者机构：Natl Res Univ Higher Sch Econ Moscow Inst Elect & Math Moscow Russia Russian Acad Sci Inst Design Problems Microelect Moscow Russia 

出 版 物：《CRYOGENICS》 (低温学)

年 卷 期：2020年第108卷

页      面：103069-103069页

核心收录：

学科分类：080705[工学-制冷及低温工程] 07[理学] 070205[理学-凝聚态物理] 08[工学] 0807[工学-动力工程及工程热物理] 0702[理学-物理学] 

基　　金：Basic Research Program of the National Research University Higher School of Economics (HSE) [TZ-99] Russian Foundation for Basic Research [18-07-00898 A] RFBR NSFC [20-57-53004] 

主　　题：JFET transistors Cryogenic temperature Low-temperature effects Compact transistor models Model parameter extraction experimental I-V characteristics Spice-like circuit simulators 

摘      要：Compact Si JFET model for SPICE circuit simulation in the extended temperature range from 373 K down to 73 K (+100 degrees C...-200 degrees C) is proposed. It is based on the standard JFET model Level = 3 (Statz model) with the full set of temperature-dependent parameters in the cryogenic temperature range. The universal procedure for model parameter extraction from I-V-characteristic measurement data at low temperature is developed. The simulation error does not exceed 10-15% in the temperature range 373 K.73 K. The JFET Low-T model is implemented in the form of a subcircuit and tested in popular SPICE-like circuit simulators: HSPICE, LTSpice, ADS, and OrCAD.