High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4:2 compressor design in CNFET technology

作     者：Avan, Amin Maleknejad, Mojtaba Navi, Keivan 

作者机构：Shahid Beheshti Univ Fac Comp Sci & Engn GC Tehran Iran Islamic Azad Univ Dept Comp Engn Sci & Res Branch Tehran Iran 

出 版 物：《IET CIRCUITS DEVICES & SYSTEMS》 (IET Circuits Devices Syst.)

年 卷 期：2020年第14卷第3期

页      面：357-368页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

主　　题：CMOS logic circuits carbon nanotube field effect transistors multiplying circuits logic design logic gates threshold logic low-power electronics field effect transistor circuits capacitors CNFET technology multioperand addition multiplication hardware high-speed hybrid designs transmission gate multiplexers low supply voltages carbon nanotube field-effect transistors entire input capacitor network frequency conditions temperature variations similar capacitive threshold logic circuits reference design high-speed energy efficient process temperature tolerant hybrid multithreshold 4:2 compressor design multithreshold logic input capacitor network Synopsys HSPICE process-voltage-temperature variations capacitive threshold logic circuits power-delay product binary multiplier uniform test bench isolated single 4:2 compressors size 32 0 nm 

摘      要：Compressors are fundamental components in multi-operand addition and multiplication hardware. The present study aims to propose several high-speed hybrid designs of 4:2 compressors which are implemented based on multi-threshold logic and transmission gate multiplexers, at low supply voltages. In order to implement these circuits, carbon nanotube field-effect transistors (CNFETs) are utilised. The division of the entire input capacitor network in the third proposed design causes the entire structure operates faster and consumes less power. All designs were simulated with Synopsys HSPICE and $32\, {\rm nm}$32nm CNFET technology in different conditions. Simulation results demonstrate the superiority of the third proposed design with regard to different load and frequency conditions. In addition, it becomes less sensitive to process, voltage and temperature variations compared to other similar capacitive threshold logic circuits. The results indicate the third proposed design outperforms the best reference design in terms of delay and power-delay product by 34 and 25%, respectively. Furthermore, the performance of each design was evaluated in a 8 x 8-bit binary multiplier as a uniform test bench, which confirmed the above results on isolated single 4:2 compressors.