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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Paolucci, Pier S. Jerraya, Ahmed A. Leupers, Rainer Thiele, Lothar Vicini, Piero ATMEL Roma INFN INFN Dip. Fisica Univ. Roma Italy TIMA INPG 46 Av. Félix Viallet 38031 Grenoble Cedex France Inst. for Integrated Signal Proc. Syst. Aachen Univ. of Technology Germany Zürich Switzerland INFN C/o Dip. Fisica Univ. Roma la Sapienza P.le Aldo Moro 5 00185 Roma Italy

ISBN: (纸本)1595933700

Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point DSP, a RISC, a DNP (Distributed Network Processor), distributed on chip memory, the POT (a set of Peripherals On Tile) plus an interface for DXM (Distributed External Memory). The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours engineering methodologies is adopted for off-chip networking and maximum system density. The SW challenge is to provide a simple and efficient programming environment for tiled architectures. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and inter-tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface. © Copyright 2006 ACM.

关键词： Embedded systems

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Architectural support for safe software execution on embedded processors

Architectural support for safe software execution on embedde...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 NEC Laboratories America Princeton NJ 08540

ISBN: (纸本)1595933700

The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. A major portion of known security attacks against software systems can be attributed to this shortcoming, including the well-known stack overflow, heap overflow, and format string attacks. Despite their limitations, the flexibility, performance, and ease of use of these languages have made them the choice of most embedded software developers. Researchers have proposed various techniques to enhance programs for memory safety;however, they are all subject to severe performance penalties, making their use impractical in most scenarios. In this paper, we present architectural enhancements to enable efficient, memory-safe execution of software on embedded processors. The key insight behind our approach is to extend embedded processors with hardware that significantly accelerates the execution of the additional computations involved in memory-safe execution. Specifically, we design custom instructions to perform various kinds of memory-safety checks and augment the instruction set of a state-of-the-art extensible processor (Xtensa from Tensilica, Inc.) to implement them. We demonstrate the application of the proposed architectural enhancements using CCured, an existing tool for type-safe retrofitting of C programs. The tool uses a type-inferencing engine that is built around strong type-safety theory and is provably safe. Simulations of memory-safe versions of popular embedded benchmarks on a cycle-accurate simulator modeling a typical embedded system configuration indicate an average performance improvement of 2.3x, and a maximum of 4.6x when using the proposed architecture. These enhancements entail minimal (less than 10%) hardware overhead to the base processor. Our approach is completely automated, and applicable to any C program, making it a promising and practi

关键词： Embedded systems

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Multi-processor system design with ESPAM

Multi-processor system design with ESPAM

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Nikolov, Hristo Stefanov, Todor Deprettere, Ed Leiden Institute of Advanced Computer Science Leiden University Netherlands

ISBN: (纸本)1595933700

For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system architectures based on a single processor. Thus, the emerging embedded system-on-Chip platforms are increasingly becoming multiprocessor architectures. As a consequence, two major problems emerge, i.e., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these platforms. Unfortunately, most of the current design methodologies and tools are based on Register Transfer Level (RTL) descriptions, mostly created by hand. Such methodologies are inadequate, because creating RTL descriptions of complex multiprocessor systems is error-prone and time *** an efficient solution to these two problems, in this paper we propose a methodology and techniques implemented in a tool called Espam for automated multiprocessor system design and implementation. Espam moves the design specification from RTL to a higher, so called system level of abstraction. We explain how starting from system level platform, application, and mapping specifications, a multiprocessor platform is synthesized and programmed in a systematic and automated way. Furthermore, we present some results obtained by applying our methodology and Espam tool to automatically generate multiprocessor systems that execute a real-life application, namely a Motion-JPEG encoder. © Copyright 2006 ACM.

关键词： Multiprocessing systems

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Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow met...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Lim, Pilok Kim, Taewhan School of Electrical Enginnering and Computer Science Seoul National University Seoul Korea Republic of

ISBN: (纸本)1595933700

Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1?C and 11.8?C lower peak temperature on the average, compared to that of the conventional low-power and thermalaware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively. © Copyright 2006 ACM.

关键词： Microprocessor chips

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hardware cryptography-embedded multimedia mobile system

Hardware cryptography-embedded multimedia mobile system

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10th World Multi-conference on systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis

作者： Fukase, Masa-aki Akaoka, Ryo Sato, Tomoaki Hirosaki Univ Dept Elect & Informat Syst Engn Hirosaki Aomori 0368561 Japan Hirosaki Univ Comp & Network Syst Ctr Hirosaki Aomori 0368561 Japan

ISBN: (纸本)9789806560680

Security aware multimedia mobility is crucial for the further progress of ubiquitous environment. Java has been promising in view of multimedia mobile features and easy treating, but this lacks simplicity in language processing and platform organization. This has resulted in the saturation of increasing the overall performance of ubiquitous network. On the other hand, user security has been really threatened due to diversified open access to the ubiquitous network, while the diversity from small devices to large machines brings about easy access anytime anywhere. Thus, ever growing ubiquitous community makes overall demands for security, speed, and power consciousness in processing large quantity of multimedia data. The key technology to answer these requirements will be a single VLSI (very large scale integration) chip processor and its software support system, We have exploited the H/S (hardware/software) codesign of a hardware cryptography-embedded multimedia mobile processor and its language processing. The processor named HCgorilla is a devised interpreter type Java CPU (central processing unit) with less power and higher throughput for multimedia cryptographic streaming. The language processing for HCgorilla includes a Java interface and parallelizing compilers. We describe in this article our recent results about the overall system of HCgorilla.

关键词： processor hardware cryptography multimedia mobile Java byte code

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Efficient exploration of bus-based system-on-chip architectures

Efficient exploration of bus-based system-on-chip architectu...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Codesign & Parallel Proc Lab Seoul 151742 South Korea Samsung Elect Yongin 446711 Gyeonggi South Korea

Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.

关键词： communication architecture design space exploration memory allocation multitask performance estimation

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A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

A unified hardware/software runtime environment for FPGA-bas...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Robert Brodersen Artem Tkachenko Hayden Kwok-Hay So Department of Electrical Engineering and Computer Science University of California Berkeley USA

This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented.

关键词： hardware Runtime environment Operating systems Kernel Application software software design Field programmable gate arrays Computer interfaces software standards File systems

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Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 707-716页

作者： Zhu, Xinping Qin, Wei Malik, Sharad Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

In multiprocessor-based system-on-chips (SOCs), optimizing the communication architecture is often as important-as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time;at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation-level concurrency maps to the microarchitectural-level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). Our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multiprocessing-element SOC prototypes. We show that, by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design.

关键词： bus design exploration multiprocessor system on-chip communication architecture (OCA) packet-switching network retargetable simulation simulator synthesis

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"It's a small world after all": NoC performance optimization via long-range link insertion

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 693-706页

作者： Ogras, Umit Y. Marculescu, Radu Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental, results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.

关键词： design automation multiprocessor system-on-chip (MP-SoC) network-on-chip (NoC) performance analysis

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TLM/network design space exploration for networked embedded systems

TLM/network design space exploration for networked embedded ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： D. Quaglia F. Fummi N. Bombieri Dipartimento di Informatica Universitá di Verona Verona Italy

This paper presents a methodology to combine Transaction Level Modeling and system/Network co-simulation for the design of networked embedded systems. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used both to drive architecture refinement and exploration and to validate the system after each refinement step. A general criterion to map functionalities to system and Network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client.

关键词： Space exploration Embedded system Internet telephony Computational modeling Computer simulation Permission Computer networks Computer architecture Mobile handsets Wireless sensor networks

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