A new search-based satisfiability (SAT) formulation that can handle entire fieldprogrammablegate array (FPGA), routing all nets concurrently is presented. the approach relies on a recently developed SAT engine that ...
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A new search-based satisfiability (SAT) formulation that can handle entire fieldprogrammablegate array (FPGA), routing all nets concurrently is presented. the approach relies on a recently developed SAT engine that uses systematic search with conflict directed nonchronological backtracking, capable of handling very large SAT instances. Preliminary experimental results suggest that this approach to FPGA routing is more viable than earlier binary decision diagram-based method.
the placement phase of the compile process and an ultrafast placement algorithm targeted to fieldprogrammablegatearrays (FPGA) are presented. the algorithm is based on a combination of multiple-level, bottom-up clu...
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the placement phase of the compile process and an ultrafast placement algorithm targeted to fieldprogrammablegatearrays (FPGA) are presented. the algorithm is based on a combination of multiple-level, bottom-up clustering and hierarchical simulated annealing. It provides superior area results over a known high-quality placement tool on a set of large benchmark circuits, when both are restricted to a short run time. In addition, operating on its fastest mode, this tool can provide an accurate estimate of the wirelength achievable with good quality placement. this can be used in conjunction with a routing predictor, to determine the routability of a given circuit on a given FPGA device.
An approach for runtime mapping is proposed that utilizes self-reconfigurability of multicontext fieldprogrammablegatearrays (FPGA) to achieve very high speedups over existing approaches. the idea is to design and ...
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An approach for runtime mapping is proposed that utilizes self-reconfigurability of multicontext fieldprogrammablegatearrays (FPGA) to achieve very high speedups over existing approaches. the idea is to design and map logic onto a multicontext FPGA that in turn maps problem instance dependent logic onto other contexts of the same FPGA. As a result, computer aided design tools need to be used just once for each problem and not once for every problem instance as is usually done.
the Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition to flexibly configurable ROM and dual...
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the Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition to flexibly configurable ROM and dual port RAM. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. the ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in boththe hardware and software domains. the architecture and features of this Embedded System Block are described.
A FPGA configuration method named configuration cloning is developed to exploit spatial and temporal regularity and locality in algorithms and architectures by copying and operating on the configuration bit-stream alr...
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A FPGA configuration method named configuration cloning is developed to exploit spatial and temporal regularity and locality in algorithms and architectures by copying and operating on the configuration bit-stream already resident in a FPGA. the method resulted in speed and power improvement over off-chip partial reconfiguration techniques, while not requiring additional interconnects and control hardware. Cloning requires only a small amount of hardware overhead. Digital signal processing applications are discussed to demonstrate the order of magnitude reductions in configuration time and power.
In this paper we present a novel coverification concept for embedded microcontrollers that satisfies industrial requirements. Based on a commercially available CPU in-circuit emulator coupled with FPGA boards, it veri...
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ISBN:
(纸本)0769507662
In this paper we present a novel coverification concept for embedded microcontrollers that satisfies industrial requirements. Based on a commercially available CPU in-circuit emulator coupled with FPGA boards, it verifies the correctness of an implementation in terms of function and timing within a real-world environment. Using our system, the software engineer can write, test and optimize programs for a chip that is not yet physically existent. In addition the system is used to obtain software module characterization data required for system partitioning. Its ability to integrate analog circuitry enables verification of the complete system-on-chip. Our methodology is fully integrated into the ASIC design flow providing ease of use and a high level of verification accuracy.
FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical a...
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FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficient silicon usage. Rather, since interconnect resources consume most of the area on these devices (often 80-90%), we can achieve more area efficient designs by allowing some LUTs to go unused - allowing us to use the dominant resource, interconnect, more efficiently. this extends the `Sea-of-gates' philosophy, familiar to mask programmablegatearrays, to FPGAs. Also introduced in this work is an algorithm for `depopulating' the gates in a hierarchical network to match the limited wiring resources.
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. the configuration compression algorithm presented in our previous paper [Hauck98c] is one efficient...
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One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. the configuration compression algorithm presented in our previous paper [Hauck98c] is one efficient technique for reducing this overhead. In this paper, we develop an algorithm for finding Don't Care bits in configurations to improve the compatibility of the configuration data. Withthe help of the Don't Cares, higher configuration compression ratios can be achieved by using our modified configuration compression algorithm. this improves compression ratios of a factor of 7, where our original algorithm only achieved a factor of 4.
In this paper an array architecture for computation of Complex Discrete Wavelet Transform has been proposed. the wavelet filter coefficients are realized using multiplier less pipelined CORDIC algorithm. the choice of...
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ISBN:
(纸本)9781581133516
In this paper an array architecture for computation of Complex Discrete Wavelet Transform has been proposed. the wavelet filter coefficients are realized using multiplier less pipelined CORDIC algorithm. the choice of pipelined CORDIC algorithm over the conventional one for realizing the filter coefficient of CDWT is hardware effective and also effects in high frequency operation. the controller unit clusters input samples into even and odd samples coming in proper sequence at each clock cycles. this clustering provides a good amount of parallelism for faster operation of the filter compared to direct filter realization. the 8-tap filter bank is implemented using array architecture, effecting in high throughput. the algorithm developed is implemented on FPGA using the Virtex XCV100 series.
A reconfigurable architecture optimized for media processing, and based on 4-bit arithmetic logic unit (ALU) and interconnect is described. Together, these allow the area devoted to configuration bits and routing swit...
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A reconfigurable architecture optimized for media processing, and based on 4-bit arithmetic logic unit (ALU) and interconnect is described. Together, these allow the area devoted to configuration bits and routing switches to be about 50% of the area of the basic CHESS array, leaving the rest available for user-visible functional units. CHESS flexibility in application mapping is largely due to the ability to feed ALU with instruction streams generated within the array, generous provision of embedded block random access memory, and the ability to trade routing switches for small memories.
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