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"It's a small world after all": NoC performance optimization via long-range link insertion

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 693-706页

作者： Ogras, Umit Y. Marculescu, Radu Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental, results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.

关键词： design automation multiprocessor system-on-chip (MP-SoC) network-on-chip (NoC) performance analysis

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TLM/network design space exploration for networked embedded systems

TLM/network design space exploration for networked embedded ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： D. Quaglia F. Fummi N. Bombieri Dipartimento di Informatica Universitá di Verona Verona Italy

This paper presents a methodology to combine Transaction Level Modeling and system/Network co-simulation for the design of networked embedded systems. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used both to drive architecture refinement and exploration and to validate the system after each refinement step. A general criterion to map functionalities to system and Network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client.

关键词： Space exploration Embedded system Internet telephony Computational modeling Computer simulation Permission Computer networks Computer architecture Mobile handsets Wireless sensor networks

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hardware-software codesign of Multimedia Embedded systems: the PeaCE

Hardware-Software Codesign of Multimedia Embedded Systems: t...

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IEEE international conference on Embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Soonhoi Ha Choonseung Lee Youngmin Yi Seongnam Kwon Young-Pyo Joo The CAP Laboratory Seoul National University South Korea

hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the peace codesign environment mainly targeting for multimedia applications with real-time constraints. Peace specifies the system behavior with a heterogeneous composition of three models of computation. The Peace environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique

关键词： Multimedia systems Embedded system hardware Computer architecture Space exploration Algorithm design and analysis software tools Computational modeling software design software performance

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Streamroller:: automatic synthesis of prescribed throughput accelerator pipelines

Streamroller:: automatic synthesis of prescribed throughput ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Scott Mahlke Kevin Fan Manjunath Kudlur Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements.

关键词： Throughput Pipelines hardware Kernel Design methodology Cost function Linear accelerators High level synthesis Algorithm design and analysis Embedded computing

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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Scott Mahlke Manjunath Kudlur Hyunchul Park Kevin Fan Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable.

关键词： hardware Acceleration Costs Algorithm design and analysis Application software Decoding Energy efficiency Accelerator architectures Computer architecture Laboratories

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Automatic run-time extraction of communication graphs from multithreaded applications

Automatic run-time extraction of communication graphs from m...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Robert P. Dick Ai-Hsin Liu Electrical Engineering and Computer Science Department Northwestern University Evanston IL USA

Embedded system synthesis, multiprocessor synthesis, and thread assignment policy design all require detailed knowledge of the runtime communication patterns among different threads or processes. Researchers have commonly relied on manual estimation, compile- time analysis, or synthetic benchmarks when developing and evaluating synthesis algorithms and thread assignment policies. In a more ideal world, it would be possible to quickly and easily determine the run-time communication properties of large commercial and academic multithreaded applications. This article describes a fully-automated method of extracting run-time communication graphs from multithreaded applications. The resulting graphs may be used to better understand, design, and synthesize application-specific hardware-software systems. The proposed graph extraction method is implemented as a module within the Simics multiprocessor simulator. It presently supports the analysis of arbitrary multithreaded applications running on the Linux operating system. This software is called CETA. It is freely available for academic and non-profit use.

关键词： Runtime Embedded system Application software Yarn Operating systems Data mining Algorithm design and analysis Computational modeling Computer architecture Linux

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hardware based frequency/voltage control of voltage frequency island systems

Hardware based frequency/voltage control of voltage frequenc...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Diana Marculescu Puru Choudhary Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

The ability to do fine grain power management via local voltage selection has shown much promise via the use of voltage/ frequency islands (VFIs). VFI-based designs combine the advantages of using fine-grain speed and voltage control for reducing energy requirements, while allowing for maintaining performance constraints. We propose a hardware based technique to dynamically change the clock frequencies and potentially voltages of a VFI system driven by the dynamic workload. This technique tries to change the frequency of a synchronous island such that it will have efficient power utilization while satisfying performance constraints. We propose a hardware design that can be used to change the frequencies of various synchronous islands interconnected together by mixed-clock/mixed-voltage FIFO interfaces. Results show up to 65% power savings for the set of benchmarks considered with no loss in throughput.

关键词： Frequency hardware Voltage control Clocks Dynamic voltage scaling Energy management Power system management Power engineering computing Power engineering and energy Throughput

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Energy minimization for real-time systems with (m, k)-guarantee

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 717-729页

作者： Niu, Linwei Quan, Gang Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Energy consumption and quality of service (QoS) are two primary concerns in the development of today's pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on hard real-time systems, a large number of practical applications and systems exhibit more soft real-time nature. In this paper, we study the problem of minimizing energy for soft real-time systems while providing a QoS guarantee. The QoS requirements are deterministically quantified with the (m, k)-constraints, which require that at least m out of any k consecutive jobs of a task meet their deadlines. In this paper, we propose a hybrid approach to achieve the dual goals of QoS guarantee and energy minimization. We first present the necessary and sufficient schedulability conditions for the static mandatory/optional workload partitioning. Then, we propose to dynamically vary the statically defined mandatory/optional partitions to accommodate dynamic run-time variations while minimizing the energy consumption. The experimental results demonstrate that our proposed techniques outperform previous work significantly in terms of both the energy savings and achieved QoS.

关键词： dynamic volage scaling (DVS) earliest deadline first (EDF) embedded system quality of service (QoS) real-time scheduling

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Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure

Efficient computation of buffer capacities for multi-rate re...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Marco Bekooij Gerard Smit Pierre Jansen Maarten Wiggers University of Twente Enschede Netherlands Philips Research Eindhoven Netherlands

A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buffers in order to control jitter. This requires the derivation of buffer capacities that both satisfy the temporal constraints as well as constraints on the buffer capacity. Existing exact solutions suffer from the computational complexity associated with the required conversion from a multi-rate dataflow graph to a single-rate dataflow graph. In this paper we present an algorithm, with linear computational complexity, that does not require this conversion and that determines close to minimal buffer capacities. The algorithm is applied to an MP3 play-back application that is mapped on our network based multi-processor system.

关键词： Real time systems Throughput Delay Control systems Jitter Computational complexity system-on-a-chip Streaming media Permission Containers

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hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

Hardware assisted pre-emptive control flow checking for embe...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sri Parameswaran Roshan G. Ragel National ICT Australia University of New South Wales Sydney NSW Australia

Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardware-assisted approaches are not scalable and therefore cannot be implemented in real embedded systems. This paper presents a scalable, cost effective and novel fault detection technique, to ensure proper control flow of a program. This technique includes architectural changes to the processor and software modifications. While architectural refinement incorporates additional instructions, the software transformation utilizes these instructions into the program flow. Applications from an embedded systems benchmark suite are used for testing and evaluation. The overheads are compared with the state of the art approach that performs the same error coverage using software-only techniques. Our method has greatly reduced overheads compared to the state of the art. Our approach increased code size by between 3.85-11.2% and reduced performance by just 0.24-1.47% for eight different industry standard applications. The additional hardware (gates) overhead in this approach was just 3.59%. In contrast, the state of the art software- only approach required 50-150% additional code, and reduced performance by 53.5-99.5% when error detection was inserted.

关键词： hardware Application software Computer errors Australia software performance Runtime Computer crashes Monitoring Embedded software Embedded system

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