Optical digitalprocessing.offers an opportunity to go beyond the speed limit of electronic computing mainly because optics, unlike electronics, is inherently suitable for highly parallel architectures. In this presen...
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Much of the work done in digitalimageprocessing.has been limited in application to black-and-white images, this being especially true of enhancement and restoration. The extension to color imageprocessing.is not tr...
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Much of the work done in digitalimageprocessing.has been limited in application to black-and-white images, this being especially true of enhancement and restoration. The extension to color imageprocessing.is not trivial; a suitable color space must be selected for a given application, and then a good processing.strategy must be devised. In fact, we doubt that any of the available color spaces will meet the needs of all types of imageprocessing. Many color imageprocessing.strategies require that only a luminance component be actually processed. In image restoration, for example, good results are achievable by processing.only the Y component of the popular NTSC transformation from RGB to YIQ components. In this paper we show that color saturation, as well as luminance, can play an important role in achieving good image enhancement. The technique proposed is simple to implement and is based on the observation that the saturation component often contains high frequency components that are not present in the luminance component. Contrast and sharpness enhancement techniques are discussed; the computer processing.algorithms are restricted to those that preserve the natural appearance of the scene. We also discuss limitations to luminance and saturation processing.caused by poor quantization of the RGB tristimulus images.
A multiprocessor-based computer graphics system called MAGIC (Multiprocessor-based All-round Graphic image Computer) is presented. It is designed to provide a fast computation environment for computer-graphics algorit...
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ISBN:
(纸本)0818608021
A multiprocessor-based computer graphics system called MAGIC (Multiprocessor-based All-round Graphic image Computer) is presented. It is designed to provide a fast computation environment for computer-graphics algorithms. MAGIC consists of high-performance processing.elements (PEs), a display buffer/controller, and a control processor, connected to each other by a sophisticated bus system. A PE has a vector processing.unit, a scalar processing.unit, and an address generator. A unique triple-bus architecture is used to ensure the overall throughput, avoiding data-transfer bottlenecks that have occurred in other machines. To obtain high-speed execution and easy programming, the PE instruction set is divided into three hierarchical groups. Experimental results show that one PE has a processing.capability more than 15 times faster than that of a VAX 11/780.
This paper briefly reviews Honeywell progress and capabilities in the development and production of Data Management Systems, Data Recording, and Automatic Target Cuers. The semiconductor technology being applied by Ho...
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ISBN:
(纸本)0892527293
This paper briefly reviews Honeywell progress and capabilities in the development and production of Data Management Systems, Data Recording, and Automatic Target Cuers. The semiconductor technology being applied by Honeywell to the DMS and autocuer circuitry is also briefly reviewed. The necessary advanced fabrication technology is all available at Honeywell's Signal processing.Technologies Center and includes VLSI and VHSIC Phase II implementations of dense high speed imageprocessing.chips. CMOS, Bipolar Enhanced MOS (BEMOS), digital Bipolar, and Linear Bipolar designs in both silicon and GaAs are used as appropriate. Progress on the algorithms needed to operate the DMS and autocuer hardware is also noted. Laboratory demonstrations of some hardware and algorithms have been done in 1986. Further development in all areas is underway for 1987 and 1988 demonstrations.
An approach to solving the speed requirements associated with modern control algorithms is to use a special kind of processor chip. digital signal processors (DSPs) are constructed to speedily perform the kinds of ari...
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An approach to solving the speed requirements associated with modern control algorithms is to use a special kind of processor chip. digital signal processors (DSPs) are constructed to speedily perform the kinds of arithmetic operations associated with digital filtering and processing. Most DSPs are built with what is called a Harvard architecture. This configuration is unlike conventional computer architectures in that it employs separate data and instruction memories that are accessed by separate buses. The benefit of this arrangement is increased speed because instructions and data can move in parallel instead of sequentially. In addition, these integrated circuits (ICs) generally carry high-speed hardware multipliers and fast on-chip memories that eliminate delays associated with shuttling information on and off chip to peripheral devices. This promotes fast program execution.
Many designers of high-end display systems use a single high-speed processor to control the frame buffer. Although such a processor is usually adequate in applications that manipulate and display images with few bit p...
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Many designers of high-end display systems use a single high-speed processor to control the frame buffer. Although such a processor is usually adequate in applications that manipulate and display images with few bit planes, this type of processor can rarely keep pace when the application deals with high-quality shaded images. For applications that require fast transformation and rendering of complex shaded images, designers can use a parallel, pipelined multi-processor architecture to achieve high throughput. The main topics are linear increase in speed, applying parallelism to drawing and rendering, and how parallelism speeds frame buffer access.
Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a fl...
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Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a flexible pipelined architecture optimized for L1 or L2-norm distance calculation, used in a wide variety of imageprocessing. The AGU chip, including 15-word register file for pointer alteration, offers a user-friendly two dimensional pointer addressing. A realtime Video Signal Processor Module (VSPM), composed of one PAU, four AGUs and memories, has been implemented for multiprocessor VSP configuration. Thanks to software control capability, various kinds of picture coding techniques can be evaluated by the system.
Presents techniques for computing multicolored polygonal masks for image analysis and computer vision applications. Basis of the procedures; Implementation of the techniques in existing pipeline image processors; Use ...
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Presents techniques for computing multicolored polygonal masks for image analysis and computer vision applications. Basis of the procedures; Implementation of the techniques in existing pipeline image processors; Use of algorithms for digital visual inspection applications.
A multiple microcomputer system for digital signal and imageprocessing.applications is presented. A simple ring structure is employed to organize the multiple microcomputers. The data flow in the ring structure is un...
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A multiple microcomputer system for digital signal and imageprocessing.applications is presented. A simple ring structure is employed to organize the multiple microcomputers. The data flow in the ring structure is unidirectional. A task can be partitioned and be distributed among the microcomputers. Pipelined execution of a task is thus possible. Implemention with the use of the TMS32010 signal processing.CPU and IBM PC is demonstrated. A design to ensure the program synchronization is also shown. A algorithm for carrying out IIR filtering is developed. Experimental results are presented.
Speech recognition algorithms employing a similarity measure between the input speech utterance and the stored reference patterns to determine recognition of a word/sentence are computationally intensive. The instanta...
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Speech recognition algorithms employing a similarity measure between the input speech utterance and the stored reference patterns to determine recognition of a word/sentence are computationally intensive. The instantaneous vocabulary size that can be handled in real-time is relatively small. This limitation can be alleviated by either using multiple programmable processors or by using special purpose hardware to handle the computation-intensive tasks. In a research environment the former approach is preferred, because improvements to the algorithm can rapidly be incorporated and their effects studied in real-time. Texas Instruments has developed a multiple-processor architecture based on the TMS32020 DSP, called Odyssey, that interfaces with Explorer, a symbolic computer. This paper addresses the issues involved in partitioning and allocating tasks in a multiple-processor environment to maximise throughput, and discusses the implementation of a grammar-driven speaker-dependent connected-word recognizer (GDCWR) as an example application that uses the power of multiple processors.
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