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Electronic Components and Technology conference (ECTC)

作者： Rathin Mandal Kazunori Yamamoto Gongyue Tang Institute of Microelectronics A*STAR (Agency for Science Technology and Research) Singapore

numerical modeling and simulation of temperature cycling test (TCT) and power cycling test (PCT) are applied to the design reliability analysis for a proposed 6-in-1 power module (PM) package. The fatigue life for both 95Sn5Sb solder interconnect and sintered Ag die attach (DA) joints under TCT and PCT conditions are calculated and compared with a reference power module package which has already passed the reliability test. The Coffin-mansion life model ductility factor is calculated from the test data for the reference power module and applied to the analysis of the fatigue life for the PM. The reliability of solder interconnect is in the same level as the reference module which passed the 1000 cycles of TCT and 50000 cycles of PCT. Sintered Ag DA joint has a very high reliability life. The structural reliability of interconnect for the proposed PM could be further enhanced by using sintered Ag as both DA and interconnect materials. Effect of package parameters such as DA and copper clip thickness are also investigated in this study. The results provided important guidelines for the PM package design.

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An adaptive simulation framework for AMS-RF test quality

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INTEGRATION-THE VLSI JOURNAL 2020年 73卷 10-17页

作者： Gutierrez, Valentin Leger, Gildas Univ Seville Inst Microlectron Sevilla CSIC Av Amer Vespucio 28 Seville 41092 Spain

Ensuring the quality of a circuit implies ensuring the quality of test. Despite the fact that performance-based testing has been the golden standard for Analog, Mixed-Signal and RF test for decades, high-reliability markets like automotive have found that functional test leaves some potential defects undetected that can produce infield failure. There is thus a push towards defect-oriented testing which, in turn, calls for an efficient defect simulation framework. This paper presents a statistical adaptive defect simulation based on likelihood-weighted random sampling to evaluate the quality of AMS-RF tests in terms of defect coverage and fault escape. The adaptive loop takes a decision at each new defect simulation on whether it is more efficient to assess the defect coverage or the fault escape rate of the test under evaluation, as a function of the desired targets for these two metrics. Several decision criteria are proposed and validated by simulation of a complete IC for different tests.

关键词： AMS-RF test Defect simulation Test evaluation Fault escape Defect coverage

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design of a real-time face detection architecture for heterogeneous systems-on-chips

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INTEGRATION-THE VLSI JOURNAL 2020年 74卷 1-10页

作者： Spagnolo, Fanny Perri, Stefania Corsonello, Pasquale Univ Calabria Dept Informat Modeling Elect & Syst Engn I-87036 Arcavacata Di Rende Italy Univ Calabria Dept Mech Energy & Management Engn I-87036 Arcavacata Di Rende Italy

Object detection represents one of the most important and challenging task in computer vision applications. Boosting-based approaches deal with computational intensive operations and they involve several sequential tasks that make very difficult developing hardware implementations with high parallelism level. This work presents a new hardware architecture able to perform object detection based on a cascade classifier in real-time and resource-constrained systems. As case study, the proposed architecture has been tailored to accomplish the face detection task and integrated within a complete heterogeneous embedded system based on a Xilinx Zynq-7000 FPGA-based System-on-Chip. Experimental results show that, thanks to the proposed parallel processing scheme and the runtime adaptable strategy to slide sub-windows across the input image, the novel design achieves a frame rate up to 125fps for the QVGA resolution, thus significantly outperforming previous works. Such a performance is obtained by using less than 10% of on-chip available logic resources with a power consumption of 377 mW at the 100 MHz clock frequency.

关键词： Integral images Face detection Image processing FPGA

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FEA simulation and modeling for fan-out package design

FEA simulation and modeling for fan-out package design

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Electronics Packaging Technology conference (EPTC)

作者： Rathin Mandal A-STAR Institute of Microelectronics

ISBN: (纸本)9798350398861

The fan-out package technology is introduced for package miniaturization, better electrical performance and lower cost. In this paper we are presenting wafer level warpage prediction followed by package stress and warpage, board level temperature cycling reliability and solder ball shear test modeling for a reliable package design. A modeling methodology for wafer level warpage is presented here with cure shrinkage material properties for polymeric materials. Cure shrinkage material property is showing around 35% more wafer level warpage than without cure shrinkage. Wafer warpage increased by 1.340mm for every 10 micron meter photo-dielectric polyamide (PI) thickness. The package stress modeling shows critical UBM (under bump metallization) stress is at the UBM neck at -50°C. Board level reliability (BLR) for temperature cycling (TC) solder fatigue life is more than 2000 cycles for a fully populated 10mm ×10mm, 0.4mm pitch, UBM SAC-Q solder. The SAC-Q solder reliability life is more than 1.5X of SAC387. The solder ball shear test FEA modeling also shows strong integrity of copper and mold compound materials and failure occurs at the bulk solder.

关键词： Semiconductor device modeling Analytical models Temperature Semiconductor device reliability Predictive models Reliability engineering Neck

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Substrate design Optimization of Fine Pitch FCCSP for Molded Underfill Void Free Evaluation

Substrate Design Optimization of Fine Pitch FCCSP for Molded...

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Electronics Packaging Technology conference (EPTC)

作者： Freedman Yen Vito Lin Yu-Po Wang Cooperate R & D Siliconware Precision Industries Co. Ltd. Tantzu Taichung Taiwan

ISBN: (纸本)9798350398861

The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and fine bump pitch (high bump density), especially when Molded Underfill (MUF) is used during transfer molding process. There is one important challenge that faced severe air void entrapment underneath the die region (air void concentrate among bumps region). Generally, the experiments involving a lot of DOE matrixes which spend a lot of time and materials (dummy die, substrate, mold compound…etc.) to solve this air void issue. As above reasons, the moldflow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of MUF FCCSP with different substrate solder mask pattern design which can reduce development cycle time before mass production. In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. There is substrate solder mask with different opening area percentage (finger like) design within die region and molding compound flow to die region that solder mask opening area with 20um depth structure to perform different melt-front behavior. From this study, we can conclude some results for improvement molding performance of FCCSP(MUF) during transfer molding process. The FCCSP(MUF) with the 65um stand-off height structure performs low air void risk due to mold compound could easily flow under die region with more flow space. In addition, mold compound also performs well melt-front flow when the substrate solder mask with opening area as 25% and opening pattern design as horizontal as flow direction that both can get more space and smooth flow underneath die region to reduce void risk during molding process.

关键词： Solid modeling Three-dimensional displays Atmospheric modeling Software microelectronics Compounds Transfer molding

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Temperature Compensation on SRAM-Based Computation in Memory Array

Temperature Compensation on SRAM-Based Computation in Memory...

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International SoC design conference, ISOCC

作者： Qibang Zang Wang Ling Goh Fei Li Lu Lu Anh Tuan Do School of EEE Nanyang Technological University Singapore Institute of Microelectronics A*STAR Singapore

ISBN: (纸本)9781665459723

Compute in memory (CIM) is a promising solution for Edge AI applications. However, previous researches on CIM focus more on performance and power efficiency (TOPS/W) improvement, while less considerations on PVT effect. In this paper, an on-chip auto-calibration technique is proposed to compensate the impact of operating temperature on the computation accuracy of the CIM array. Our simulation showed that the proposed technique offer the same BL discharge slope across different temperatures from -40 ° C to 120 °C with little INL/DNL degradation when compared to the conventional design. In normal computation mode, the proposed design achieves 310TOPS/W and after compensation the inference accuracy on MNIST dataset is improved to 96% even under different temperatures.

关键词： Performance evaluation Degradation Temperature distribution Computational modeling Common Information Model (computing) Software Discharges (electric)

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Circuitry of Micro-Power JFET and CMOS Input Differential Stages for Op-Amps on Silicon and Wide-Band Semiconductors

Circuitry of Micro-Power JFET and CMOS Input Differential St...

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Siberian conference on Control and Communications (SIBCON)

作者： Vladislav Chumakov Nikolay Prokopenko Alexey Titov Don State Technical University Rostov-on-Don Russia Institute for Design Problems in Microelectronics of RAS Don State Technical University Rostov-on-Don Zelenograd Russia Southern Federal University Rostov-on-Don Russian Federation

ISBN: (纸本)9781665476294

The study presents an analysis of universal JFET and CMOS differential stages (DS) circuits. Such cascades provide a smaller range of transistor currents (10-100 $\mu$A) compared to classical cascades. The described DSs are implemented on combined process technologies, and therefore can be designed on JFET, BJT or CMOS chips. In addition, gallium arsenide, diamond gallium nitride, thin-film TFT and silicon carbide transistors. A computer simulation of the static modes of the developed DSs and their current dependences is presented. The results of GaAs DS modeling and its frequency dependence are presented.

关键词： Semiconductor device modeling Silicon carbide Gallium arsenide Diamonds CMOS technology Silicon JFETs

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A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level

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INTEGRATION-THE VLSI JOURNAL 2020年 72卷 13-20页

作者： Saraza-Canflanca, P. Diaz-Fortuny, J. Castro-Lopez, R. Roca, E. Martin-Martinez, J. Rodriguez, R. Nafria, M. Fernandez, F., V Univ Seville Inst Microelect Sevilla CSIC IMSECNM Seville Spain UAB Elect Engn Dept REDEC Grp Barcelona Spain

In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.

关键词： Time-dependent variability TDV Random telegraph noise RTN Bias temperature instability BTI Characterization Hot-carrier injection HCI CMOS Reliability simulation

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modeling advanced spintronic based magnetoresistive memory

Modeling advanced spintronic based magnetoresistive memory

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International conference on Microwave & THz Technologies, Wireless Communications and OptoElectronics (IRPhE 2022)

作者： S. Fiorentini M. Bendra J. Ender T. Hadámek W. J. Loch N. P. Jθrstad R. Orio W. Goes S. Selberherr V. Sverdlov Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics TU Wien Austria Institute for Microelectronics TU Wien Austria Silvaco Europe Ltd. Cambridge United Kingdom

Spintronic based magnetoresistive memory shows an increasing potential in replacing conventional charge based memory for stand-alone and embedded applications. Accurate simulation tools, providing a comprehensive evaluation of the spin torques and magnetization dynamics in structures with several ferromagnetic and nonmagnetic metal layers separated by tunnel barriers, are required to design advanced magnetoresitive memory cells. We demonstrate that the coupled spin and charge drift-diffusion transport approach, extended to describe magnetic tunnel junctions and augmented with temperature, is suitable to describe complex magnetoresitive memory cells with two reference layers controlled by spin torques.

关键词： ferromagnetic materials magnetic multilayers magnetisation magnetoelectronics magnetoresistive devices MRAM devices spin polarised transport tunnelling magnetoresistance

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Multidomain modeling for Reliability Evaluation of Devices and Microsystems Using Verilog-A

Multidomain Modeling for Reliability Evaluation of Devices a...

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International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： Jean-Baptiste Kammerer Maroua Garci Achraf Kaï d Fabrice Roqueta Fabien Pr&#x00E9 galdiny Luc H&#x00E9 brard ICube Strasbourg France STMicroelectronics Tours France

ISBN: (数字)9788363578220

ISBN: (纸本)9781665461764

With the continuous increase in integration density, the dissipated power density has reached a critical level and thermal issues are now a major concern. Currently, evaluating the thermal behavior of a chip is generally done thanks to a finite element method software. However, this approach is complex, time consuming and sometimes even not feasible. Thereby, the need for a user-friendly tool designed to evaluate the temperature distribution inside an integrated system through standard circuit simulation arises. Analog hardware description languages (AHDL) offer the opportunity to manipulate thermal quantities thus allowing to perform electrothermal simulations in a standard microelectronics CAD environment. Taking advantage of the capabilities of these AHDL, a general method consisting in layout driven meshing for thermal modeling of the chip associated to electrothermal compact modeling of devices has been developed. The resulting tool which is fully integrated in the Cadence environement is able to generate an electrothermal netlist suitable to SPICE-like simulators. To address large system simulations, a high-level electrothermal modeling method has been developed, allowing to perform full-chip simulations. Recently, the tool has been adapted to power electronics industry needs. It is able to address reliability issues such as overheating, hot spot detection, thermal drift or even delamination.

关键词： Performance evaluation Micromechanical devices Heating systems Solid modeling Adaptation models Behavioral sciences Reliability

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