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信息技术 2023年第4期47卷 179-184页

作者：李萌冯文楠郝先人冯曦胡毅唐晓柯北京智芯微电子科技有限公司北京100192

射频识别电子标签(RFID)芯片具有命令多、状态多、Memory容量大、分区多等特点,这些特点增加了芯片仿真验证的工作量和难度。为了解决Verilog语言搭建的传统电子标签验证平台测试例数量众多和验证场景不全面的问题,基于通用验证方法学(U... 详细信息

射频识别电子标签(RFID)芯片具有命令多、状态多、Memory容量大、分区多等特点,这些特点增加了芯片仿真验证的工作量和难度。为了解决Verilog语言搭建的传统电子标签验证平台测试例数量众多和验证场景不全面的问题,基于通用验证方法学(UVM)搭建了一套随机化可重用的电子标签验证平台。相比于传统验证平台,新的验证平台采用事务级建模和分层的激励产生机制,结构清晰,验证用例简洁,运行效率较高,并且功能覆盖率可以达到100%,代码覆盖率也有所提升。

关键词：通用验证方法学射频识别电子标签验证平台分层序列功能覆盖率驱动

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Finite Element Method Approach to MRAM modeling

Finite Element Method Approach to MRAM Modeling

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Proceedings of the International Convention MIPRO

作者： M. Bendra J. Ender S. Fiorentini T. Hadamek R.L. de Orio W. Goes V. Sverdlov S. Selberherr Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic Institute for Microelectronics TU Wien Vienna Austria Silvaco Europe Ltd. Cambridge United Kingdom

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is among the most promising candidates for emerging memories. Thus, reliable simulation tools are mandatory to provide an important aid for understanding and improving the design of such devices. In this work we are concerned with the simulation of STT-MRAM. The well-known Landau-Lifshitz-Gilbert (LLG) equation describes the magnetization dynamics. Since we are dealing with STT-MRAM, an additional torque term must be added to the LLG equation. The torque acting on the magnetization is generated by the nonequilibrium spin accumulation due to the electric current flowing through the structure. The partial differential LLG equation with the additional torque computed from the spin accumulation is solved using the highly efficient finite element method (FEM). We implemented several time integration schemes using an open-source FEM library. In order to verify and calibrate the FEM implementation, we compared it to a finite difference method (FDM) implementation used as a reference. By properly tailoring the time integration scheme and the time step size, almost identical simulation results as with the FDM are achieved. Proper calibration is essential in order to simulate a more realistic multi-layer structure with a composite switching layer consisting of ferromagnetic layers separated by nonmagnetic buffers.

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Analogue Realization of a Fully Tunable Fractional-Order PID Controller for a DC Motor

Analogue Realization of a Fully Tunable Fractional-Order PID...

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International Conference on microelectronics, ICM

作者： Georgios Pappas Vassilis Alimisis Christos Dimas Paul P. Sotiriadis National Technical University of Athens Greece

ISBN: (数字)9781728196640

ISBN: (纸本)9781728196657

This paper explores a new integrated-circuit architecture of an analog, active, tunable and selectively fractional or integer-order PID controller using operational amplifiers. Controller's major parameters are tuned via appropriate DC currents to the desired values. The proposed architecture is validated in a case study of a DC motor control and it can be used as a building block in industrial and commercial control systems. Circuit and physical design (layout) have been done in TSMC 90nm CMOS process. Extensive circuit and post-layout simulation are carried out using the Cadence IC design.

关键词： Sensitivity Architecture simulation Control systems DC motors Integrated circuit modeling Tuning

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Synapse design based on memristor

Synapse design based on memristor

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IEEE International Conference on design & Test of Integrated Micro & Nano-Systems (DTS)

作者： Mouna Elhamdaoui Khaoula Mbarek Sami Ghedira Faten Ouaja Rziga Kamel Besbes Microelectronics & Instrumentation Lab. University of Monastir Monastir Tunisia Centre for Research on Microelectronics & Nanotechnology Sousse Technology Park Microelectronics & Instrumentation Lab. University of Monastir Monastir Tunisia

ISBN: (数字)9781728154299

ISBN: (纸本)9781728154305

The memristor is a passive two-terminal electrical device where its conductance is accurately modulated either by the charge or the flux flowing through it. In this paper, we implement a simple and flexible Verilog-A memristor model in order to perform synaptic functions, including both long-term potentiation LTP and long-term depression LTD, to subsequently validate the Hebbian learning algorithm (STDP). Our simulation results reveal the I-V characteristic of a Ta 2 O 5 -based memristive device. We prove that the Verilog-A model is able to reproduce the conductance change in the STDP learning method. Therefore, the use of memristors as synapses in neuromorphic circuits may potentially provide high connectivity and high-density area for efficient computation.

关键词： Memristors Synapses Hardware design languages Computer architecture Switches Integrated circuit modeling microelectronics

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Effect of P+ region design on the fabrication of 6500 V 4H-SiC JBS diodes

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Journal of Crystal Growth 2020年 530卷 125317-000页

作者： Sang, Ling Tian, Lixin Li, Jialin Niu, Yingxi Jin, Rui State Key Laboratory of Advanced Power Transmission Technology Global Energy Interconnection Research Institute Co. Ltd. Beijing102209 China School of Microelectronics Xidian University Xi'an710071 China

We studied the effect of P+ region design on the simulation and fabrication of 6500 V 4H-SiC JBS diodes. There existed a deviation of 0.9 μm in P+ region design between theoretical simulation and actual device during the fabrication. We mainly attributed this change of P+ region design to the implantation spreading and the mask etching processes. The simulation fitted well with the measured results considering the broadening of 0.9 μm of P+ region. According to the analysis, we calibrated the simulation and successfully fabricated the 6500 V/40A 4H-SiC JBS diodes. The simulation fitted very well with the performance of fabricated device. © 2019

关键词： Etching

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The Discussion of the Typical BEOL design Rules from 3 nm to 2 nm Logic Process with EUV and High NA EUV Lithography

The Discussion of the Typical BEOL Design Rules from 3 nm to...

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Advanced Patterning Solutions (IWAPS), International Workshop on

作者： Qiang Wu Yanli Li Xiaona Zhu Shaofeng Yu School of Microelectronics Fudan University Shanghai China

ISBN: (纸本)9781665420808

With the purpose to continuously improve the speed and density of chip operation, the size of the transistors and the spacing between the transistors have been shrinking, following what is called the Moore's law in the last 40 years. When the logic process node reaches 3 nm or smaller, the room for the improvement in FinFET architecture is no longer available. Complementary FET (CFET) structure has been proposed to continue the performance improvement through area reduction with the NMOS placed on top of the PMOS. In this paper, through the use of a self-developed simulation program, we study the typical design rule patterns of the back-end-of-line (BEOL) metal and via layers from 3 nm and 2 nm logic processes. From the development roadmap of transistors, it can be seen that the pitch of BEOL metal layer from 3 nm CFET is around 20~24 nm, which can be realized by 0.33 NA Extreme Ultra-Violet (EUV) lithography with double pattering scheme using self-aligned litho-etch-litho-etch (SALELE) process. Taking 40~48 nm as the anchoring pitch, in order to obtain enough process windows, we make detailed design rules for some typical 2D patterns (such as dense pattern, semi-dense pattern, isolated pattern, Tip-to- Tip (TtT) and Tip-to-Line (TtL) patterns, etc.), and we can also calculate the minimum area of isolated patterns. The pitch of BEOL metal layer from 2 nm FinFET is assumed to be 14~18 nm, for which we have done process window simulation under both 0.33 NA and 0.55 NA EUV processes. We will compare both exposure processes on exposure energy, exposure latitude, line width roughness, and defect density originated from photon absorption stochastics. We will present a study on both the process cost and performance for the 3 and 2 nm photo processes.

关键词： Semiconductor device modeling Extreme ultraviolet lithography Costs Ultraviolet sources Moore's Law Metals Stochastic processes

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design, simulation and Implementation of Very Compact Dual-band Microstrip Bandpass Filter for 4G and 5G Applications 16

Design, Simulation and Implementation of Very Compact Dual-b...

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16th International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD) / 15th Conference on PhD Research in microelectronics and Electronics (PRIME)

作者： Al-Yasir, Yasir I. A. Parchin, Naser Ojaroud Abdulkhaleq, Ahmed Hameed, Khalid Al-Sadoon, Mohammed Abd-Alhameed, Raed Univ Bradford Fac Engn & Informat Bradford W Yorkshire England SARAS Technol Ltd Leeds W Yorkshire England

ISBN: (纸本)9781728112015

This article proposes a very compact planer open-loop bandpass filter (BPF) with asymmetric frequency response and covering the 2.5 to 2.6 GHz and 3.6 to 3.7 GHz spectrum for 4G and 5G applications, respectively. The microstrip BPF employs four open-loop ring resonators with 50 Omega tapped lines for input and output ports. To achieve sharper cut-off frequencies, one infinite and three finite transmission zeros are successfully generated on the upper and lower edges of the 4G and 5G passbands. The utilization of the planer four-section resonators not only reduces the size of the structure, but also provides either positive or negative cross-coupling. The cross-coupling coefficients between the resonators are optimized to resonate at the required frequency with proper bandwidth. The reported BPF is designed and optimized using CST software, and is implemented on a Rogers RO3010 substrate with a relative dielectric constant of 10.2 and a very compact size of 11x9x1.27 mm(3). Good agreement is achieved between the simulated and measured results.

关键词： microstrip filter bandpass open-loop 4G 5G applications compact CST

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VIRTUAL PROTOTYPING AND simulation OF ELECTRO-THERMAL SYSTEMS 20

VIRTUAL PROTOTYPING AND SIMULATION OF ELECTRO-THERMAL SYSTEM...

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20th International Conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in microelectronics and Microsystems (EuroSimE)

作者： Hauck, Torsten Jha, Vibhash NXP Semicond Germany Schatzbogen 7 D-81829 Munich Germany

ISBN: (纸本)9781538680407

Virtual prototyping is the way forward to shorten development cycles and deliver optimized design solutions for semiconductor components and electronic modules. It allows us to make virtual experiments for devices that have never been built before. We can predict safe operating areas and on the other hand identify critical use conditions. Key requirement for virtual prototyping is an efficient and accurate simulation model that does consider multiple physical domains (e.g. thermal, electrical, mechanical) along with complex 3-D structures. The focus of the current paper is to present an efficient simulation flow for prediction of three-dimensional temperature fields at transient operating conditions with multiple heat sources and associated thermal cross talk at component and system levels. In what follows, we will demonstrate the virtual assembly of an electronic control unit (ECU) and its transient thermal simulation in time domain. We will decompose the unit into its major components for which fast mathematical models will be derived by means of model order reduction techniques. We will then create a reduced mathematical model of the entire ECU by simply interconnecting all component models at predetermined I/Os. We will demonstrate a stimulus-response analysis of the interconnected system and a subsequent result expansion path for 3-D visualization of temperature fields. Finally, we will compare simulation results of the reduced system model with the corresponding full-scale finite element model.

关键词： Mathematical model Finite element analysis Transmission line matrix methods Transistors Interconnected systems Heating systems Integrated circuit modeling

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modeling and Application of Flexible Electronics Packaging 1

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2019年

作者： YongAn Huang Zhouping Yin Xiaodong Wan

ISBN: (数字)9789811336270

ISBN: (纸本)9789811336263

This book systematically discusses the modeling and application of transfer manipulation for flexible electronics packaging, presenting multiple processes according to the geometric sizes of the chips and devices as well as the detailed modeling and computation steps for each process. It also illustrates the experimental design of the equipment to help readers easily learn how to use it. This book is a valuable resource for scholars and graduate students in the research field of microelectronics

关键词： Electronics and microelectronics, Instrumentation Optical and Electronic Materials Manufacturing, Machines, Tools, Processes Theoretical and Applied Mechanics simulation and modeling

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3D simulation Technique To Predict Failure of Photo Marks Interaction 17

3D Simulation Technique To Predict Failure of Photo Marks In...

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IEEE Workshop on microelectronics and Electron Devices (WMED)

作者： Kotti, Radhakrishna Micron Technol Boise ID 83707 USA

ISBN: (纸本)9781538605714

This paper presents a 3D simulation technique to predict the interaction failure of scribe photo marks. Device scaling for increased speed and density, coupled with advanced memory architectures is increasing the fabrication complexity. These process changes are accompanied by additional masking levels with multiple layers to align. Each new masking level requires photo marks such as registration, alignment and metrology for their processing. The process is first optimized for the die layout leaving the construction of photo marks vulnerable due to their unique patterning requirements. This may cause some unintended process interactions creating registration or alignment failures. So, a validation technique guided by modeling mask and process interaction is proposed to avoid unintended structural results. The method proposed is implemented and verified using a 3D simulator on alignment and registration marks. The results obtained from the proposed method clearly show that any new unintended process interaction can be identified at the pre-silicon stage and rectified before reticle manufacture improving the learning time and cost.

关键词： Photo lithography 3D simulation Scribe Marks Mask Interaction design Rule Checks Registration marks Alignment marks Scatterometry marks

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