This paper explores the transformative role of softcore processors in integratedcircuit (IC) design, emphasizing their reconfigurability and rapid prototyping advantages over traditional hardcore processors. It provi...
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This paper presents a voltage regulator with current-sinking capability designed as a low-side supply for an HV gate driver circuit. The proposed novel topology regulates an input voltage from IOV to 60V into a stable...
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This paper presents a novel approach to voice manipulation that focuses on techniques such as pitch shifting, timbre alteration, and speech synthesis. The system is designed to operate in real-time, ensuring seamless ...
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The micro-pattern gas detectors (MPGDs) offer high spatial and time resolution and a large active area, among which the micro-resistive WELL ( mu RWELL) detector has received increasing attention in recent years due t...
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The micro-pattern gas detectors (MPGDs) offer high spatial and time resolution and a large active area, among which the micro-resistive WELL ( mu RWELL) detector has received increasing attention in recent years due to its simple structure, low material budget, and high counting rate capability. It is, therefore, proposed as an important option for the low-mass Inner TracKer (ITK) detector in the future Super Tau-Charm Facility (STCF). Considering the high luminosity in the STCF, the innermost ITK layer requires a new high-rate, low-noise, and low-power readout application-specific integratedcircuit (ASIC). The first version of the prototype ASIC integrates a 32-channel analog processing circuit. In the charge-sensitive amplifier (CSA), the bulk-driven current mirror is adopted to reduce the headroom voltage and lower the supply voltage to 0.8 V, thereby reducing power consumption while maintaining the same channel thermal noise and transconductance. In addition, an equivalent "cold resistor" circuit is proposed to achieve both fast recovery and low noise. This ASIC has been fabricated in a 0.18- mu m CMOS process, and a series of tests has been performed. The equivalent noise charge (ENC) is measured to be 487 e(- )+ 29.2 e(-) /pF with a charge measurement range of 40 fC and a peaking time of 25 ns. Meanwhile, the maximum repetition rate capability per channel at a 70-ns charge collection time is up to 4 MHz, while the power consumption is only 1.93 mW per channel, resulting in a figure of merit (FOM) of only 0.29 pJ.
This paper presents the design and analysis of a Single Master Single Slave Serial Peripheral Interface (SPI) system implemented on an FPGA. SPI is a communication protocol that enables data transfer between devices b...
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This paper presents the design and analysis of a Monolithic Microwave integratedcircuit (MMIC) based balanced power amplifier (BPA) for K-band frequencies (18 GHz-22 GHz). The amplifier is built using a 0.15 µm ...
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The rapid advancement of integratedcircuit (IC) technology has increased the demand for efficient and effective VLSI optimization methods. This paper presents a systematic literature review as well as a conceptual fr...
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The rapid advancement of integratedcircuit (IC) technology has increased the demand for efficient and effective VLSI optimization methods. This paper presents a systematic literature review as well as a conceptual framework for optimizing placement and routing congestion estimation and control in VLSI design. This paper review existing algorithms, optimization techniques for placement and routing, congestion estimation, and control mechanisms. The goal is to comprehend the advantages, disadvantages, and applicability of these algorithms in addressing VLSI design problems. Furthermore, the research proposal seeks to create a comprehensive approach that incorporates various optimization techniques to improve the overall performance of integratedcircuits. The estimation and control of routing congestion receive special attention because it has a significant impact on signal flow and overall circuit quality. The preferred programming platform for implementing the proposed methodology is the MATLAB technical computing language, along with the required toolboxes. This research aims to contribute to the advancement of efficient and reliable IC designs by addressing the key challenges in VLSI design using an optimized placement and routing framework.
In order to address the numerous drawbacks of traditional experimental examinations, an examination system for circuit experiment courses has been developed. The system adopts a modular design and is divided into thre...
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This work introduces an open-source, Process technology-agnostic framework for hierarchical circuit netlist, layout, and Reinforcement Learning (RL) optimization. The layout, netlist, and optimization python API is fu...
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The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integratedcircuits (ICs) to mitigate the noise inherent with switching. A new technology c...
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