The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet p...
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The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmablelogic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new fieldprogrammable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten's complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.
This paper represents possible approaches to cyber security assurance for implementation the configuration process of fieldprogrammable Gates Array (FPGA) based platform for safety critical applications. It also cont...
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ISBN:
(纸本)9781509046898
This paper represents possible approaches to cyber security assurance for implementation the configuration process of fieldprogrammable Gates Array (FPGA) based platform for safety critical applications. It also contains results of conducted analysis for secure configuration process in existing platforms, similar in terms of functionality, but based on different technologies. Protection concepts for RadICS Platform Configuration Tool (RPCT) and appropriate license key file are presented. Requirements to key management system are provided considering RPCT features.
This paper presents the design of reversible fault tolerant architecture of logic elements of LUT ( look-up table) based fieldprogrammable Gate Array ( FPGA). The proposed logic elements are master slave Flip Flop, D...
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ISBN:
(纸本)9781467387002
This paper presents the design of reversible fault tolerant architecture of logic elements of LUT ( look-up table) based fieldprogrammable Gate Array ( FPGA). The proposed logic elements are master slave Flip Flop, D-Latch and multiplexer. A new 4x4 and a new 6x6 fault tolerant reversible gates are proposed for designing efficient reversible fault tolerant D-latch, master slave Flip Flop and multiplexer, respectively. The design of the proposed logic elements achieve the improvement of 41.67% in terms of number of gates compared to the best known existing approach. Besides, the proposed logic elements outperform the best existing technology by 13.33% and 27.27% in terms of quantum cost and unit delay, respectively. Finally, the efficiency of the proposed elements are clarified by implementing an n-bit adder using the proposed Configurable logic Block ( CLB) of FPGA with 60.9% power savings and 23.56% delay minimization.
In modern SRAM based fieldprogrammable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a h...
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ISBN:
(纸本)9781509056026
In modern SRAM based fieldprogrammable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. To reduce the area as well as the number of configuration bits, we have further explored and improved a previously proposed novel FPGA architecture which allows sharing of LUTs memory tables among NPN equivalent functions. A recently proposed high performance Boolean matching algorithm has been employed to perform NPN classification. Furthermore, a new clustering technique has also been proposed which packs NPN equivalent functions together inside a Configurable logic Block (CLB). Consequently, this work explores the SRAM-table sharing approach for a range of LUT sizes (4-7), while varying the cluster sizes (4-16). Experimental results on MCNC benchmark circuits set show an overall area reduction of -3.7% while maintaining the same critical path delay.
Approximate computing is a new design paradigm targeting at error-tolerant applications. By allowing a little amount of inaccuracy in the computation, it could significantly reduce circuit area and power consumption. ...
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ISBN:
(纸本)9781509015597
Approximate computing is a new design paradigm targeting at error-tolerant applications. By allowing a little amount of inaccuracy in the computation, it could significantly reduce circuit area and power consumption. Several logic synthesis methods for approximate computing were proposed recently. However, these methods are mainly aimed at ASIC designs. In this work, we propose a novel approximate logic synthesis method targeting at the FPGA design. We exploit the flexibility of lookup tables and propose a method that combines wire removal and local function change. The experimental results showed that our method produces better results than the state-of-the-art approximate logic synthesis method adapted to FPGA designs. Moreover, it can be combined with the state-of-the-art method to further improve the design quality.
In this paper, we propose the China-US international data placement laboratory (iDPL) based on an inter-continental testbed for data placement research. iDPL is able to support various data placement research due to i...
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ISBN:
(纸本)9781538616291
In this paper, we propose the China-US international data placement laboratory (iDPL) based on an inter-continental testbed for data placement research. iDPL is able to support various data placement research due to its scalability and flexibility in deploying the experiments in the real network environment. The core design of iDPL leverages reliable workflow management and lightweight I/O protocol to allow complex experiment setup and on-the-fly experiment deployment. It is also extensible to plugin different network profiling tools such as iperf. We expect the powerful measurement capability of iDPL promotes research study on the intelligent data placement policies which adapt to the uncertainty of the wide-area network and guarantee the quality of service (QoS) of the big data applications. As a case study, we setup a set of data placement experiments to measure the end-to-end network performance constantly among several sites between China and US using different data placement tools. The experiments have been running for more than one year, and its measurement data is public available (http://***:8080/). We believe the measurement data is valuable for both network and big data researchers to understand the performance disparity between the raw network and the actual data placement, which provides useful insights to design big data applications with performance awareness. We encourage more researchers to deploy their own data placement experiments on iDPL, expediting the research direction of intelligent data placement with real network environment.
Clock glitches are useful in hardware security applications, where systems are tested for vulnerabilities emerging from fault attacks. Usually a precisely timed and controlled glitch signal is employed. However, this ...
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Clock glitches are useful in hardware security applications, where systems are tested for vulnerabilities emerging from fault attacks. Usually a precisely timed and controlled glitch signal is employed. However, this requires complex generators and deep knowledge about the system under attack. Therefore we present a novel approach on clock glitch fault attacks that replaces the single precise glitch by a fuzzy glitch signal. We propose a compact FPGA design for fuzzy clock glitch generation, that is based on mixing two adjustable ring oscillators of different frequencies. The combination of these oscillators creates a glitch containing random and high frequency signal components. We show on the basis of a practical implementation on a Spartan-3E, that the proposed method is able to generate the desired fuzzy clock glitch. We verified experimentally, that the fuzzy clock glitch succeeds in error injection on an STM32F030, an ARM CORTEX-M0 based microcontroller. Our results demonstrate that the fuzzy glitch is an adequate solution for fault injection.
programmablelogic Controllers (PLCs) are specialized computing systems for the control and monitoring of distributed industrial devices. Aiming for a highly connected industrial Internet-of-Things (IoT) ecosystem, PL...
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ISBN:
(纸本)9781467391467
programmablelogic Controllers (PLCs) are specialized computing systems for the control and monitoring of distributed industrial devices. Aiming for a highly connected industrial Internet-of-Things (IoT) ecosystem, PLCopen OPC Unified Architecture (UA) specification has been released. This paper presents the implementation and evaluation of a PLCopen OPC-UA software component for industrial control systems. A preliminary evaluation of the developed software has been conducted to analyze the performance of OPC-UA client FBs.
Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in sa...
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Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g. aging and wear-out effects) also have negative impacts on reliability of modern circuits. Furthermore, as recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems, for avionic and space applications, certain fault tolerant strategy must be applied to guarantee system reliability throughout application lifetime. In this paper, we focus on two aspects: testing for System-on-Chip/System-on-programmable-Chip by exploiting debug infrastructures and analysis and mitigation of Single Event Effects on FPGA devices.
In recent years, Augmented Reality (AR) started transitioning from an experimental technology to a more mature area, with new types of applications in entertainment, marketing, education, retail, transportation, manuf...
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In recent years, Augmented Reality (AR) started transitioning from an experimental technology to a more mature area, with new types of applications in entertainment, marketing, education, retail, transportation, manufacturing, construction, and other industries. One of the main challenges for AR-based field service tools is to help users to correctly locate company's assets and infrastructure in the field. This paper presents an AR system using private maps to find company's assets to support field workforce tasks. The AR system is based on fuzzy logic mechanisms to provide the user with directions for asset location by comparing his/her current position with assets' location in real-time. Auditory and visual feedback is provided via a head mounted display (HMD), enhancing user's perception to achieve human augmentation.
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