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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"
834 条 记 录,以下是701-710 订阅
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Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfligurable FPGAs  7
Hardware-software co-synthesis of low power real-time distri...
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7th Asia and South Pacific Design Automation Conference/15th international Conference on VLSI Design
作者: Shang, L Jha, NK Princeton Univ Dept EE Princeton NJ 08544 USA
In this paper, we present a multi-objective hardware-software co-synthesis system for multi-rate, real-time, low power distributed embedded systems consisting of dynamically reconfigurable FPGAs, processors, and other... 详细信息
来源: 评论
Architecting to Achieve a Billion Requests Per Second Throughput on a Single Key-Value Store Server Platform  15
Architecting to Achieve a Billion Requests Per Second Throug...
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acm/IEEE 42nd Annual international symposium on Computer Architecture (ISCA)
作者: Li, Sheng Lim, Hyeontaek Lee, Victor W. Ahn, Jung Ho Kalia, Anuj Kaminsky, Michael Andersen, David G. Seongil, O. Lee, Sukhan Dubey, Pradeep Intel Labs Santa Clara CA 95054 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Seoul Natl Univ Seoul 151 South Korea
Distributed in-memory key-value stores (KVSs), such as memcached, have become a critical data serving layer in modern Internet-oriented datacenter infrastructure. Their performance and efficiency directly affect the Q... 详细信息
来源: 评论
CJS: Custom Jacobi Solver  2018
CJS: Custom Jacobi Solver
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9th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)
作者: Cross, Andreea-Ingrid Guo, Liucheng Luk, Wayne Salmon, Mark Imperial Coll London London England Univ Cambridge Cambridge England
The classic Jacobi method, widely used for solving linear systems, is slow, especially when dealing with large matrices. This paper proposes a Custom Jacobi Solver (CJS) for large-scale linear systems. It is based on ... 详细信息
来源: 评论
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA  08
Implementation of a double-precision multiplier accumulator ...
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21st symposium on Integrated Circuits and Systems Design, SBCCI 2008
作者: Barros, Abner Correa Medeiros, Victor Wanderley Costa Souza, Viviane Lucy Santos Nascimento, Paulo Sérgio Brando Mazer, Ângelo L. Barbosa, João P. F. Neves, Bruno P. Santos, Ismael De Lima, Manoel Eusebio Informatics Center Recife-PE Brazil Centro de Pesquisa da Petrobrás CENPES Petrobrás - Rio Brazil
Recently, the manufactures of supercomputers have made use of FPGAs to accelerate scientific applications [16][17]. Traditionally, the FPGAs were used only on non-scientific applications. The main reasons for this fac... 详细信息
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Universal Switch-Module Design for Symmetric-Array-Based FPGAs
Universal Switch-Module Design for Symmetric-Array-Based FPG...
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proceedings of the acm international symposium on field-programmable gate arrays, FPGA
作者: Yao-Wen Chang D.F. Wong C.K. Wong University of Technology Austin TX USA Department of Computer Science Chinese University of Hong Kong Hong Kong China
A switch module M with W terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (the number of nets on each side of M is at most W) is simultaneously routable through... 详细信息
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Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only)  10
Towards 5ps resolution TDC on a dynamically reconfigurable F...
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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays
作者: Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada
This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with sli... 详细信息
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Model-Based Design of A Real-time Context-Aware Speech Enhancement System on an FPGA-SoC  20
Model-Based Design of A Real-time Context-Aware Speech Enhan...
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20th international symposium on Computer Architecture and Digital Systems, CADS 2020
作者: Azadi, Alireza Attarzadeh-Niaki, Seyed-Hosein Shekofteh, Yasser Computer Science and Engineering Shahid Beheshti University G.C. Tehran Iran
Modern Implementation platforms are suitable for realizing complex adaptive systems that require the system to adjust its behavior to satisfy variable design goals. A prominent example is context-aware systems that ar... 详细信息
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FPGA and ASIC Implementation and Comparison of Multipliers  3
FPGA and ASIC Implementation and Comparison of Multipliers
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3rd international symposium on Devices, Circuits and Systems, ISDCS 2020
作者: Neyaz, Salwa Yasmeen Saxena, Itisha Alam, Naushad Rahman, Syed Atiqur Department of Electronics Engineering Aligarh India
The multipliers find extensive use in today's digital world and are even fundamental components in many signal processing applications. This paper presents the implementation and comparison of three types of 4-bit... 详细信息
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Embedded Models Realization Platform in IoT  5
Embedded Models Realization Platform in IoT
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5th IEEE international symposium on Smart and Wireless Systems within the international Conferences on Intelligent Data Acquisition and Advanced Computing Systems, IDAACS-SWS 2020
作者: Khropatyi, Oleksandr Lohinov, Oleh Kazymyr, Volodymyr Chernihiv Polytechnic National University 95 Shevchenko Str. Chernihiv14035 Ukraine
The concept of the Internet of Things is generally regarded as a phenomenon capable of rebuilding economic and social processes, excluding the need for human participation from part of actions. Cyber-physical systems,... 详细信息
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Techniques for FPGA Implementation of Video Compression Systems
Techniques for FPGA Implementation of Video Compression Syst...
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proceedings of the acm international symposium on field-programmable gate arrays, FPGA
作者: B. Schoner J. Villasenor S. Molloy Rajeev Jain Department of Electrical Engineering University of California Los Angeles CA USA
Real-time video compression is a challenging subject for FPGA implementation because it typically has a large computational complexity and requires high data throughput. Previous implementations have used parallel ban... 详细信息
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