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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"
834 条 记 录,以下是701-710 订阅
排序:
Configuration cloning: Exploiting regularity in dynamic DSP architectures
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 81-89页
作者: Park, S.R. Burleson, W. Univ of Massachusetts Amherst United States
A FPGA configuration method named configuration cloning is developed to exploit spatial and temporal regularity and locality in algorithms and architectures by copying and operating on the configuration bit-stream alr... 详细信息
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Reconfigurable arithmetic array for multimedia applications
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 135-143页
作者: Marshall, Alan Stansfield, Tony Kostarnov, Igor Vuillemin, Jean Hutchings, Brad Hewlett Packard Lab Bristol United Kingdom
A reconfigurable architecture optimized for media processing, and based on 4-bit arithmetic logic unit (ALU) and interconnect is described. Together, these allow the area devoted to configuration bits and routing swit... 详细信息
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Hybrid product term and LUT based architectures using embedded memory blocks
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 13-16页
作者: Heile, Frank Leaver, Andrew Altera Corp San Jose CA United States
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition to flexibly configurable ROM and dual... 详细信息
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Don't care discovery for FPGA configuration compression
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 91-98页
作者: Li, Zhiyuan Hauck, Scott Northwestern Univ Evanston IL United States
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. The configuration compression algorithm presented in our previous paper [Hauck98c] is one efficient... 详细信息
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Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 69-78页
作者: DeHon, Andre Univ of California at Berkeley Berkeley CA United States
FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical a... 详细信息
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Configuration caching vs data caching for striped FPGAs
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 206-214页
作者: Deshpande, Deepali Somani, Arun K. Tyagi, Akhilesh Iowa State Univ Ames IA United States
Striped FPGA, or pipeline-reconfigurable FPGA provides hardware virtualization by supporting fast run-time reconfiguration. In this paper we show that the performance of striped FPGA depends on the reconfiguration pat... 详细信息
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New high density and very low cost reprogrammable FPGA architecture
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 3-12页
作者: Kaptanoglu, Sinan Bakker, Greg Kundu, Arun Corneillet, Ivan Ting, Ben Actel Corp Sunnyvale United States
A new reprogrammable FPGA architecture is described which is specifically designed to be of very low cost. It covers a range of 35 K to a million usable gates. In addition, it delivers high performance and it is synth... 详细信息
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Exploiting FPGA-features during the emulation of a fast reactive embedded system
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 235-242页
作者: Weiss, Karlheinz Steckstor, Thorsten Koch, Gernot Rasenstiel, Wolfgang Univ of Tuebingen Tuebingen Germany
This paper presents the emulation of an embedded system with hard real time constraints and response times of about 220 μs. We show that for such fast reactive systems, the software overhead of a Real Time Operating ... 详细信息
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Innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 17-26页
作者: Agrawal, Om Chang, Herman Sharpe-Geisler, Brad Schmitz, Nick Nguyen, Bai Wong, Jack Tran, Giap Fontana, Fabiano Harding, Bill Vantis Corp Sunnyvale CA United States
This paper describes the Vantis VF1 FPGA architecture, an innovative architecture based on 0.25 u (drawn) (0.18 u Leff)/4-metal technology. It was designed from scratch for high performance, routability and ease-of-us... 详细信息
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Methodology for fast FPGA floorplanning
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 47-56页
作者: Emmert, John M. Bhatia, Dinesh Univ of Cincinnati Cincinnati United States
Floorplanning is an important problem in FPGA circuit mapping. As FPGA capacity grows, new innovative approaches will be required for efficiently mapping circuits to FPGAs. In this paper we present a macro based floor... 详细信息
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