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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfligurable FPGAs 7

Hardware-software co-synthesis of low power real-time distri...

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7th Asia and South Pacific Design Automation Conference/15th international Conference on VLSI Design

作者： Shang, L Jha, NK Princeton Univ Dept EE Princeton NJ 08544 USA

ISBN: (纸本)0769514413

In this paper, we present a multi-objective hardware-software co-synthesis system for multi-rate, real-time, low power distributed embedded systems consisting of dynamically reconfigurable FPGAs, processors, and other system resources. We use an evolutionary algorithm based framework for automatically determining the quantity and type of different system resources, and then assigning tasks to different processing elements (PEs) and task communications to communication links. For FPGAs, we propose a two-dimensional, multi-rate cyclic scheduling algorithm, which determines task priorities based on real-time constraints and reconfiguration overhead information, and then schedules tasks based on the resource utilization and reconfiguration condition in both space and time. The FPGA scheduler is integrated in a list-based system scheduler. To the best of our knowledge, this is the first multi-objective co-synthesis system, which uses dynamically, reconfigurable devices to synthesize a distributed embedded system, to target simultaneous optimization of system price and power. Experimental results indicate that our method can reduce schedule length by an average of 41.0% and reconfiguration power by an average of 46.0% compared to the previous method. It also yields multiple system architectures which trade off system price and power under real-time constraints.

关键词： field programmable gate arrays (FPGA)

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Architecting to Achieve a Billion Requests Per Second Throughput on a Single Key-Value Store Server Platform 15

Architecting to Achieve a Billion Requests Per Second Throug...

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acm/IEEE 42nd Annual international symposium on Computer Architecture (ISCA)

作者： Li, Sheng Lim, Hyeontaek Lee, Victor W. Ahn, Jung Ho Kalia, Anuj Kaminsky, Michael Andersen, David G. Seongil, O. Lee, Sukhan Dubey, Pradeep Intel Labs Santa Clara CA 95054 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Seoul Natl Univ Seoul 151 South Korea

ISBN: (纸本)9781450334020

Distributed in-memory key-value stores (KVSs), such as memcached, have become a critical data serving layer in modern Internet-oriented datacenter infrastructure. Their performance and efficiency directly affect the QoS of web services and the efficiency of datacenters. Traditionally, these systems have had significant overheads from inefficient network processing, OS kernel involvement, and concurrency control. Two recent research thrusts have focused upon improving key-value performance. Hardware-centric research has started to explore specialized platforms including FPGA5 for KVSs;results demonstrated an order of magnitude increase in throughput and energy efficiency over stock memcached. Software-centric research revisited the KVS application to address fundamental software bottlenecks and to exploit the full potential of modern commodity hardware;these efforts too showed orders of magnitude improvement over stock memcached. We aim at architecting high performance and efficient KVS platforms, and start with a rigorous architectural characterization across system stacks over a collection of representative KVS implementations. Our detailed full-system characterization not only identifies the critical hardware/software ingredients for high-petformance KVS systems, but also leads to guided optimizations atop a recent design to achieve a record setting throughput of 120 million requests per second (MRPS) on a single commodity server. Our implementation delivers 9.2X the performance (RPS) and 2.8X the system energy efficiency (RPS/watt) of the best-published FPGA-based claims. We craft a set of design principles for future platform architectures, and via detailed simulations demonstrate the capability of achieving a billion RPS with a single server constructed following our principles.

关键词： field programmable gate arrays (FPGA)

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CJS: Custom Jacobi Solver 2018

CJS: Custom Jacobi Solver

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9th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Cross, Andreea-Ingrid Guo, Liucheng Luk, Wayne Salmon, Mark Imperial Coll London London England Univ Cambridge Cambridge England

ISBN: (纸本)9781450365420

The classic Jacobi method, widely used for solving linear systems, is slow, especially when dealing with large matrices. This paper proposes a Custom Jacobi Solver (CJS) for large-scale linear systems. It is based on a column-wise Jacobi step operation which allows for increased dependence distance, enabling deep pipelining. Our solver allows customisation at run time between the classic Jacobi method and its more convergence efficient-counterpart, the weighted Jacobi method. It can be dynamically scaled to multiple FPGAs by appropriately partitioning the matrix data among the FPGAs. After evaluating our solver on a number of different datasets, CJS proves to be up to 71 times faster when comparing an 8-FPGA solution with a 12-core CPU C++ implementation.

关键词： field programmable gate arrays (FPGA)

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Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA 08

Implementation of a double-precision multiplier accumulator ...

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21st symposium on Integrated Circuits and Systems Design, SBCCI 2008

作者： Barros, Abner Correa Medeiros, Victor Wanderley Costa Souza, Viviane Lucy Santos Nascimento, Paulo Sérgio Brando Mazer, Ângelo L. Barbosa, João P. F. Neves, Bruno P. Santos, Ismael De Lima, Manoel Eusebio Informatics Center Recife-PE Brazil Centro de Pesquisa da Petrobrás CENPES Petrobrás - Rio Brazil

ISBN: (纸本)9781605582313

Recently, the manufactures of supercomputers have made use of FPGAs to accelerate scientific applications [16][17]. Traditionally, the FPGAs were used only on non-scientific applications. The main reasons for this fact are: the floating-point computation complexity;the FPGA logic cells are not sufficient for the scientific cores implementation;the cores complexity prevents them to operate on high frequencies. Nowadays, the increase of specialized blocks availability in complex operations, as sum and multiplier blocks, implemented directly in FPGA and, the increase of internal RAM blocks (BRAMs) have made possible high performance systems that use FPGA as a processing element for scientific computation [2]. These devices are used as co-processors that execute intensive computation. The emphasis of these architectures is the exploration of parallelism present on scientific computation operations and data reuse. In major of these applications, the scientific computation uses, in general, operations of big floating-point dense matrices, which are normally operated by MACs. In this work, we describe the architecture of an accumulative multiplier (MAC) in double precision floating-point, according to IEEE-754 standard and we propose the architecture of a multiplier of matrices that uses developed instances of the MACs and explores the reuse of data through the use of the BRAMs (Blocks of RAM internal to the FPGAs) of a Xilinx Virtex 4 LX200 FPGA. The synthesis results showed that the implemented MAC could reach a performance of 4GFLOPs. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Universal Switch-Module Design for Symmetric-Array-Based FPGAs

Universal Switch-Module Design for Symmetric-Array-Based FPG...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： Yao-Wen Chang D.F. Wong C.K. Wong University of Technology Austin TX USA Department of Computer Science Chinese University of Hong Kong Hong Kong China

A switch module M with W terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (the number of nets on each side of M is at most W) is simultaneously routable through M. In this paper, we present a class of universal switch modules. Each of our switch modules has 6W switches and switch-module flexiblity three (Fs = 3). We prove that no switch module with less than 6W switches can be universal. We also compare our switch modules with those used in the Xilinx XC4000 family FPGA's and the anti-symmetric switch modules (with Fs = 3^1) suggested by [Flexibility of interconnection structures for field-programmable gate arrays]. Although these two kinds of switch modules also have Fs = 3 and 6W switches, we show that they are not universal. Based on combinatorial counting techniques, we show that each of our universal switch modules can accommodate up to 25% more routing instances, compared with the XC4000-type one of the same size. Experimental results demonstrate that our universal switch modules improve routability at the chip level. Finally, our work also provides a theoretical insight into the important observation by Rose and Brown [Flexibility of interconnection structures for field-programmable gate arrays] that Fs = 3 is often sufficient to provide high routability.

关键词： field programmable gate arrays

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Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only) 10

Towards 5ps resolution TDC on a dynamically reconfigurable F...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada

ISBN: (纸本)9781605589114

This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.

关键词： field programmable gate array time-to-digital converter vernier method dynamic reconfiguration

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Model-Based Design of A Real-time Context-Aware Speech Enhancement System on an FPGA-SoC 20

Model-Based Design of A Real-time Context-Aware Speech Enhan...

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20th international symposium on Computer Architecture and Digital Systems, CADS 2020

作者： Azadi, Alireza Attarzadeh-Niaki, Seyed-Hosein Shekofteh, Yasser Computer Science and Engineering Shahid Beheshti University G.C. Tehran Iran

ISBN: (纸本)9781728181110

Modern Implementation platforms are suitable for realizing complex adaptive systems that require the system to adjust its behavior to satisfy variable design goals. A prominent example is context-aware systems that are capable of automatically adapting their operations according to the dynamic system context. This work introduces a model-based design flow for a context-aware FPGA-SoC-based system in the speech enhancement domain. The proposed design flow implements the adaptive context-awareness by exploiting the runtime reconfiguration feature of the state-of-the-art FPGA-SoC devices. By employing the proposed design flow and architecture, a context-aware speech enhancement application can be implemented in such a way that it is able to change its own processing algorithm to meet runtime goals and can lead to the area reduction of the FPGA by using one hardware-accelerated algorithm at a time. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA and ASIC Implementation and Comparison of Multipliers 3

FPGA and ASIC Implementation and Comparison of Multipliers

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3rd international symposium on Devices, Circuits and Systems, ISDCS 2020

作者： Neyaz, Salwa Yasmeen Saxena, Itisha Alam, Naushad Rahman, Syed Atiqur Department of Electronics Engineering Aligarh India

ISBN: (纸本)9781728165646

The multipliers find extensive use in today's digital world and are even fundamental components in many signal processing applications. This paper presents the implementation and comparison of three types of 4-bit and 8-bit multipliers i.e. Array, Wallace and Baugh Wooley. The implementation is done on both the FPGA and ASIC to compare the designs. The FPGA implementation is done on NEXYS 4 DDR which is equipped with Xilinx Artix-7 FPGA. The ASIC implementation is done using Cadence and Standard Cell Library 90 nm gpdk (generic process design kit). The results indicate that the Baugh Wooley incurs the minimum delay in the FPGA implementation while as the Wallace tree incurs minimum Power Delay Product in the ASIC implementation. The Baugh Wooley is the least area consuming architecture for both the FPGA and the ASIC implementation. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Embedded Models Realization Platform in IoT 5

Embedded Models Realization Platform in IoT

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5th IEEE international symposium on Smart and Wireless Systems within the international Conferences on Intelligent Data Acquisition and Advanced Computing Systems, IDAACS-SWS 2020

作者： Khropatyi, Oleksandr Lohinov, Oleh Kazymyr, Volodymyr Chernihiv Polytechnic National University 95 Shevchenko Str. Chernihiv14035 Ukraine

ISBN: (纸本)9781728199603

The concept of the Internet of Things is generally regarded as a phenomenon capable of rebuilding economic and social processes, excluding the need for human participation from part of actions. Cyber-physical systems, in turn, provide a conceptual paradigm for representing transformation of various types of information and telecommunication technologies and an environment that provides both-exchange of information between components and the stable operation of all embedded systems in various conditions of control and management of mechanisms. This article begins with an overview of the main proposals in the field of the Internet of Things and cyber-physical systems, based on the experience of the authors in various fields related to fundamental concepts, technologies and techniques such as high-quality interaction between IoT and CPS, High Level Architecture, E-networks, model-oriented control paradigm and solutions of ARM and FPGA. A rational approach is to combine the benefits of available technologies and implement a platform of embedded models based on this data with the participation of new solutions. Finally, an optimal choice of architecture and input points for the further implementation of the embedded models realization platform in IoT are described and discussed. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Techniques for FPGA Implementation of Video Compression Systems

Techniques for FPGA Implementation of Video Compression Syst...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： B. Schoner J. Villasenor S. Molloy Rajeev Jain Department of Electrical Engineering University of California Los Angeles CA USA

Real-time video compression is a challenging subject for FPGA implementation because it typically has a large computational complexity and requires high data throughput. Previous implementations have used parallel banks of FPGAs or DSPs to meet these requirements. Using design techniques that maximize FPGA utilization, we have implemented two video compression systems, each of which uses a single FPGA. In the first system, algorithmic optimizations are made to create a low-complexity implementation that exploits the in-system programmability of the FPGA. This low-complexity implementation performs well, but is limited to a single compression algorithm. In the second system, the FPGA is augmented with an external, low-complexity, video signal processor (VSP.) This combination of ASIC and FPGA is flexible enough to implement four common compression algorithms, and powerful enough to execute them in real time.

关键词： field programmable gate arrays Video compression Compression algorithms Computational complexity Throughput Digital signal processing Signal processing algorithms Signal processing Application specific integrated circuits Real time systems

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