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international conference on hardware/software codesign and system synthesis (CODES)

作者： Christoph Schumacher Gerd Ascheid Heinrich Meyr Rainer Leupers Hans van Someren Manuel Hohenauer Institute for Integrated Signal Processing Systems RWTH Aachen University Germany Associated Compiler Experts bv Amsterdam Netherlands

Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequent concern about retargetable compilers, though, is their lack of machine-specific code optimization techniques in order to achieve highest code quality. While this problem is partially inherent to the retargetable compilation approach, it can be circumvented by designing flexible, configurable code optimization techniques that apply to a certain range of target architectures. This paper focuses on target machines with SIMD instruction support which is widespread in embedded processors for multimedia applications. We present an efficient and quickly retargetable SIMD code optimization technique that is integrated into an industrial retargetable C compiler. Experimental results for the Philips Trimedia processor demonstrate that the proposed technique applies to real-life target machines and that it produces code quality improvements close to the theoretical limit.

关键词： Optimizing compilers Application specific processors Design optimization VLIW Pipeline processing Computer architecture Computer aided instruction Concurrent computing Application software Permission

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Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies

Design space exploration of real-time multi-media MPSoCs wit...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sudarshan Banerjee Nikil Dutt Nalini Venkatasubramanian Minyoung Kim School of Information and Computer Sciences University of California Irvine CA USA

Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogenous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized - our framework also includes energy reduction techniques utilizing dynamic power management. Experimental results on a realistic multi-mode multi-media terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.

关键词： Space exploration Real time systems Multimedia systems system-on-a-chip Intellectual property Libraries Dynamic scheduling Energy management Power system management Costs

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Application specific forwarding network and instruction encoding for multi-pipe ASIPs

Application specific forwarding network and instruction enco...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hui Guo Sri Parameswaran Aleksandar Ignjatovic Swarnalatha Radhakrishnan School of Computer Science and Engineering University of New South Wales Sydney Australia

Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instruction encoding schemes for multi-pipe Application Specific Instruction-Set Processors (ASIPs). Forwarding is a popular technique to reduce data hazards in the pipeline to improve performance and is applied in almost all modern processor designs; but it is very area expensive. Instruction encoding schemes have a direct impact on code size; an efficient encoding method can lead to a small instruction width, and hence reducing the code size. We propose application specific techniques to reduce forwarding networks and instruction widths for ASIPs with multiple pipelines. By these design techniques, it is possible to reduce area, code size, and even power consumption (due to reduced area), without costing any performance. Our experiments, on a set of benchmarks using the proposed customization approaches show that, on average, there are 27% savings on area, 30% on leakage power, 16.7% on code size, and at the same time, performance even improves by 4% because of the reduced clock period.

关键词： Encoding Application specific processors Pipelines Hazards Embedded system Registers Costs Application software Computer science Design engineering

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"It's a small world after all": NoC performance optimization via long-range link insertion

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 693-706页

作者： Ogras, Umit Y. Marculescu, Radu Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental, results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.

关键词： design automation multiprocessor system-on-chip (MP-SoC) network-on-chip (NoC) performance analysis

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Integrated analysis of communicating tasks in MPSoCs

Integrated analysis of communicating tasks in MPSoCs

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Matthias Ivers Rolf Ernst Simon Schliecker Institute of Computer and Communication Network Engineering Technical University of Braunschweig Germany

Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication networks, basic operations of every embedded application pose a challenge for precise system analysis. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures either focus on system level and allow only limited task models, or focus on activities inside a component, abstracting system level influences by over estimations. In this paper, we identify feedbacks of the system behavior that directly or indirectly impact local execution. To tackle these complex interactions we present a novel technique to integrate an extended component level scheduling analysis with refined system level approaches. Bringing the different levels of abstraction together allows the analysis of a new class of interacting applications and architectures - which could not be addressed on a single level alone. On the component level, we investigate two scheduling behaviors more closely, namely stalling during external requests, and allowing context-switches to other tasks that are ready. For both, we present a precise response time analysis. Finally, we compare the scheduling techniques with respect to real-time requirements.

关键词： Delay Coprocessors Performance analysis Communication networks Timing Real time systems system analysis and design Feedback Processor scheduling Permission

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Architectural support for safe software execution on embedded processors

Architectural support for safe software execution on embedde...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Niraj K. Jha Srivaths Ravi Anand Raghunathan Divya Arora Department of Electrical Engineering Princeton University Princeton NJ USA NEC Laboratories of America Inc. Princeton NJ USA

The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. Despite their limitations, the flexibility, performance, and ease of use of these languages have made them the choice of most embedded software developers. Researchers have proposed various techniques to enhance programs for memory safety; however, they are all subject to severe performance penalties, making their use impractical in most scenarios. In this paper, we present architectural enhancements to enable efficient, memory-safe execution of software on embedded processors. The key insight behind our approach is to extend embedded processors with hardware that significantly accelerates the execution of the additional computations involved in memory-safe execution. Specifically, we design custom instructions to perform various kinds of memory-safety checks and augment the instruction set of a state-of-the-art extensible processor (Xtensa from Tensilica, Inc.) to implement them. We demonstrate the application of the proposed architectural enhancements using CCured, an existing tool for type-safe retrofitting of C programs. The tool uses a type-inferencing engine that is built around strong type-safety theory and is provably safe. Simulations of memory-safe versions of popular embedded benchmarks on a cycle-accurate simulator modeling a typical embedded system configuration indicate an average performance improvement of 2.3 times, and a maximum of 4.6 times, when using the proposed architecture. These enhancements entail minimal (less than 10%) hardware overhead to the base processor. Our approach is completely automated, and applicable to any C program, making it a promising and practical approach for addressing the growing security and reliability concerns in embedded software.

关键词： Embedded software software safety Security hardware Computer languages software reliability Acceleration Embedded computing Engines Embedded system

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Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

Data reuse driven energy-aware MPSoC co-synthesis of memory ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Nikil Dutt Ilya Issenin University of California Irvine CA USA

The memory subsystem of a complex multiprocessor systems- on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP- based co-synthesis technique, a mixed ILP-based traditional two- step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach.

关键词： Memory architecture Time division multiple access Multiprocessing systems Energy consumption Throughput Permission Energy efficiency Algorithm design and analysis Merging Data analysis

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SHAPES:: a tiled scalable software hardware architecture platform for embedded systems

SHAPES:: a tiled scalable software hardware architecture pla...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Rainer Leupers Lothar Thiele Ahmed A. Jerraya Piero Vicini Pier S. Paolucci Dip. Fisica Roma Italy TIMA INPG Grenoble France Inst. for Integrated Signal Proc. Syst. Aachen University of Technology Germany Computer Eng. and Networks Lab. Swiss Federal Institute of Technology Switzerland C/o Dip. Fisica Univ. Roma La Sapienza INFN Roma Italy

Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point DSP, a RISC, a DNP (Distributed Network Processor), distributed on chip memory, the POT (a set of Peripherals On Tile) plus an interface for DXM (Distributed External Memory). The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours engineering methodologies is adopted for off-chip networking and maximum system density. The SW challenge is to provide a simple and efficient programming environment for tiled architectures. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and inter- tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface.

关键词： Shape Embedded software hardware Computer architecture Embedded system Tiles Network-on-a-chip system-on-a-chip CMOS technology Wires

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B2Sim:: a fast micro-architecture simulator based on basic block characterization

B2Sim:: a fast micro-architecture simulator based on basic b...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Massoud Pedram Kimish Patel Wonbok Lee Department of Electrical Engineering University of Southern California Los Angeles CA USA

State-of-the-art architectural simulators support cycle accurate pipeline execution of application programs. However, it takes days and weeks to complete the simulation of even a moderate- size program. During the execution of a program, program behavior does not change randomly but changes over time in a predictable/periodic manner. This behavior provides the opportunity to limit the use of a pipeline simulator. More precisely, this paper presents a hybrid simulation engine, named B 2 Sim for (cycle-characterized) Basic Block based Simulator, where a fast cache simulator e.g., sim-cache and a slow pipeline simulator e.g., sim-outorder are employed together. B 2 Sim reduces the runtime of architectural simulation engines by making use of the instruction behavior within executed basic blocks. We have integrated B 2 Sim into SimpleScalar and have achieved on average a factor of 3.3 times speedup on the SPEC2000 benchmark and Media-bench programs compared to conventional pipeline simulator while maintaining the accuracy of the simulation results with less than 1% CPI error on average.

关键词： Pipelines Phase detection Analytical models Engines Permission Runtime Maintenance Measurement techniques Power system reliability Performance analysis

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Creation and utilization of a virtual platform for embedded software optimization:: an industrial case study

Creation and utilization of a virtual platform for embedded ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jeong-Taek Kong Bum-Seok Yoo Donghyun Song Hye Jeong Nam Jaehyung Hwang Janghwan Kim Sangwoo Lee SooKwan Eo Sungjoo Yoo Kyu-Myung Choi HoonSang Jin Jeongeun Kim Sheayun Lee Sungpack Hong CAE Team System LSI Division CAE Team System LSI Division Samsung Electronics Company Limited South Korea Flash Software Group Memory Division Samsung Electronics Company Limited South Korea Flash Software Group Memory Division Storage Team System LSI Division Samsung Electronics Company Limited South Korea Storage Team System LSI Division HDD Development Group Storage Division Samsung Electronics CO. LTD South Korea Mobile SW Platform Samsung Electronics CO. LTD South Korea

Virtual platform (ViP), or ESL (electronic system level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e. g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.

关键词： Embedded software Computer industry system-level design Hard disks Timing Accuracy Programming Design optimization Analytical models Performance analysis

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