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ARCTIC: Approximate Real-Time computing in a Cache-Conscious Multicore Environment

IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第10期43卷 2944-2957页

作者： Saha, Sangeet Chakraborty, Shounak Agarwal, Sukarn Sjalander, Magnus McDonald-Maier, Klaus D. Univ Essex Embedded & Intelligent Syst Lab Colchester CO4 3SQ England Norwegian Univ Sci & Technol Dept Comp Sci N-7034 Trondheim Norway Indian Inst Technol Mandi Sch Comp & Elect Engn Suran 175005 India

Improving result-accuracy in approximate computing (AC)-based time-critical systems, without violating power constraints of the underlying circuitry, is gradually becoming challenging with the rapid progress in technology scaling. The execution span of each AC real-time tasks can be split into a couple of parts: 1) the mandatory part, execution of which offers a result of acceptable quality, followed by 2) the optional part, which can be executed partially or completely to refine the initially obtained result in order to increase the result-accuracy, while respecting the time constraint. In this article, we introduce a novel hybrid offline-online scheduling strategy, ARCTIC, for AC real-time tasks. The goal of real-time scheduler of ARCTIC is to maximize the results-accuracy (QoS) of the task set with opportunistic shedding of the optional part, while respecting system-wide constraints. During execution, ARCTIC retains exclusive copy of the private cache blocks only in the local caches in a multicore system and no copies of these blocks are maintained at the other caches, and improves performance (i.e., reduces execution-time) by accumulating more live blocks on-chip. Combining offline scheduling with the online cache optimization improves both QoS and energy efficiency. While surpassing prior arts, our proposed strategy reduces the task rejection rate by up to 25%, whereas enhances QoS by 10%, with an average energy-delay-product gain of up to 9.1%, on an 8-core system.

关键词： Task analysis Quality of service Real-time systems Processor scheduling Runtime Arctic Optimal scheduling Approximate computing (AC) cache management energy efficiency QoS improvement real-time systems

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IEEE transactions on Sustainable computing Special Issue on Sustainability of Fog/Edge computing systems

IEEE TRANSACTIONS ON SUSTAINABLE COMPUTING

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IEEE transactions ON SUSTAINABLE computing 2022年第2期7卷 248-249页

作者： Taheri, Javid Dustdar, Schahram Villari, Massimo Univ Karlstad Dept Math & Comp Sci S-65188 Karlstad Sweden Vienna Univ Technol TU Wien Inst Informat Syst Engn A-1040 Vienna Austria Univ Messina Dept Math & Comp Sci I-98122 Messina Italy

The papers in this special section focus on sustainability of edge computing systems. Edge computing is an emerging architectural and technical approach aimed at addressing various shortcomings in traditional cloud computing paradigms and responding to today's constantly increasing data-demanding services such as Internet-of-Things, 5G embedded artificial intelligence and smart cities. In Fog/Edge computing, nodes at the edge of a network are equipped with processing, storage, networking, etc. capabilities to take over several tasks that were used to be sent to cloud services. Pre-filtering and aggregation of data as well as online processing and actuation are sample procedures envisaged/dedicated to fog/ edge nodes.

关键词： Special issues and sections Edge computing Cloud computing Sustainable development Virtualization 5G mobile communication

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SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous systems-on-Chip

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ACM transactions on embedded computing systems 2023年第5期22卷 1-22页

作者： Clair, Judicael Eichler, Guy Carloni, Luca P. Columbia Univ Dept Comp Sci Mudd Bldg500 W 120th St New York NY 10027 USA

Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed with limited concerns to the problem of integrating it with other components in a heterogeneous System-on-Chip (SoC). Building on a state-of-the-art reconfigurable neuromorphic architecture, we present the design of a neuromorphic hardware accelerator equipped with a programmable interface that simplifies both the integration into an SoC and communication with the processor present on the SoC. To optimize the allocation of on-chip resources, we develop an optimizer to restructure existing neuromorphic models for a given hardware architecture, and perform design-space exploration to find highly efficient implementations. We conduct experiments with various FPGA-based prototypes of many-accelerator SoCs, where Linux-based applications running on a RISC-V processor invoke Pareto-optimal implementations of our accelerator alongside third-party accelerators. These experiments demonstrate that our neuromorphic hardware, which is up to 89x faster and 170x more energy efficient after applying our optimizer, can be used in synergy with other accelerators for different application purposes.

关键词： Neuromorphic computing machine learning spiking neural network

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Special Issue: "Approximation at the Edge"

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ACM transactions on embedded computing systems 2023年第4期22卷 1-4页

作者： Bosio, Alberto Dolecek, Lara Kourfali, Alexandra Parameswaran, Sri Savino, Alessandro Univ Lyon CNRS Guy CollongueCPE LyonINLUMR5270 ECLINSA LyonUCBL 36 Ave Guy de Collongue F-69134 Ecully France Univ Calif Los Angeles Dept Elect & Comp Engn 7400 Boelter Hall Los Angeles CA 90095 USA Univ Stuttgart ITI Pfaffenwaldring 47 D-70569 Stuttgart Germany Univ Sydney Sch Elect Engn Bldg Sydney Australia Politecn Torino Dept Control & Comp Engn Corso Duca degli Abruzzi 24 I-10129 Turin Italy

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Faster than Fast: Accelerating Oriented FAST Feature Detection on Low-end embedded GPUs

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ACM transactions on embedded computing systems 2025年第3期24卷 1-22页

作者： Chang, Qiong Chen, Xinyuan Li, Xiang Wang, Weimin Miyazaki, Jun School of Computing Institute of Science Tokyo Meguro Tokyo Japan International School of Information Science and Engineering Dalian University of Technology Liaoning Dalian China School of Electronic Science and Engineering Nanjing University Jiangsu Nanjing China

The visual-based SLAM (Simultaneous Localization and Mapping) is a technology widely used in applications such as robotic navigation and virtual reality, which primarily focuses on detecting feature points from visual images to construct an unknown environmental map and simultaneously determines its own location. It usually imposes stringent requirements on hardware power consumption, processing speed, and accuracy. Currently, the ORB (Oriented FAST and Rotated BRIEF)-based SLAM systems have exhibited superior performance in terms of processing speed and robustness. However, they still fall short of meeting the demands for real-time processing on mobile platforms. This limitation is primarily due to the time-consuming Oriented FAST calculations accounting for approximately half of the entire SLAM system. This article presents two methods to accelerate the Oriented FAST feature detection on low-end embedded GPUs. These methods optimize the most time-consuming steps in Oriented FAST feature detection: FAST feature point detection and Harris corner detection, which is achieved by implementing a binary-level encoding strategy to determine candidate points quickly and a separable Harris detection strategy with efficient low-level GPU hardware-specific instructions. Extensive experiments on a Jetson TX2 embedded GPU demonstrate an average speedup of over 7.3 times compared to widely used OpenCV with GPU support. This significant improvement highlights its effectiveness and potential for real-time applications in mobile and resource-constrained environments. © 2025 Copyright held by the owner/author(s). Publication rights licensed to ACM.

关键词： Edge detection

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Checkpointing Models for Tasks of Different Types

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ACM transactions ON MODELING AND PERFORMANCE EVALUATION OF computing systems 2024年第3期9卷 1-23页

作者： Ezhilchelvan, Paul Mitrani, Isi Newcastle Univ Sch Comp Newcastle Upon Tyne England

A server subject to random breakdowns and repairs offers services to incoming jobs whose lengths are highly variable. A checkpointing policy is in operation, aiming to protect against possibly lengthy recovery periods by backing up the current state at periodic checkpoints. The problem of how to choose a checkpointing interval to optimise performance is addressed by analysing a general queueing model which includes breakdowns, repairs, back-ups and recoveries. Exact solutions are obtained under both Markovian and non-Markovian assumptions. Numerical experiments illustrate the conditions where checkpoints are useful and where they are not, and, in the former case, quantify the achievable benefits.

关键词： M/G/1 queue embedded Markov chains server vacations checkpoint optimisation

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A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators

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ACM transactions on embedded computing systems 2023年第4期22卷 1-31页

作者： Tsounis, Ioannis Agiakatsikas, Dimitris Psarakis, Mihalis Univ Piraeus Karaoli & Dimitriou 80 Piraeus 18534 Greece

Approximate computing Techniques (ACTs) take advantage of resilience computing applications to trade off among output precision, area, power, and performance. ACTs can lead to significant gains at affordable costswhen efficiently implemented on Field Programmable Gate Array- (FPGA) based accelerators. Although several novel ACTs works have been proposed for FPGA accelerators, their applicability to high-assurance systems has not been explored as much. ACTs are becoming necessary in many critical Edge computing systems, such as self-driving cars and Earth observation satellites, to increase computational efficiency. However, an important question comes to mind when targeting critical systems: Does ACT optimization negatively affect the reliability of the system and how can one find optimal design architectures that blend classic mitigation techniques like Triple Modular Redundancy with approximation- and precise-based arithmetic hardware units to achieve the best possible computational efficiency without compromising dependability? This work aims to solve this research problem by introducing a Design Space Exploration (DSE) methodology that employs ACTs in arithmetic units of the design and identifies Pareto-optimal microarchitectures that balance all relevant gains of ACTs, such as area, speed, power, failure rate, and precision, by inserting the correct amount of approximation in the design. In a nutshell, our DSE methodology has formulated the DSE with a Multi-Objective Optimization Problem (MOP). Each Pareto-optimal solution of our tool finds which arithmetic units of the design to implement with precise and approximate circuits and which units to selectively triplicate to remove single points of failure that compromise system reliability below acceptable thresholds. We also suggest another formulation of the DSE into a Single-Objective constraint Optimization Problem (ScOP) producing a single optimal point, and that the user may demand, as a less time-consuming

关键词： Approximate computing Techniques approximate adders FPGAs Pareto-optimal fault tolerance JPEG DCT selective-TMR

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FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第6期43卷 1650-1662页

作者： Dou, Yuqin Wang, Chenghua Waris, Haroon Woods, Roger Liu, Weiqiang Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 211106 Peoples R China Natl Univ Comp & Emerging Sci Elect Engn Dept Islamabad 44000 Pakistan Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast BT9 5AH North Ireland

Current artificial intelligence and data science applications typically require complex computations and massive amounts of data handling, presenting unprecedented challenges for embedded platforms. Approximate computing has emerged as the most promising design technique to address this issue, by providing a potential performance increase, while sacrificing accuracy within an acceptable range. Approximate arithmetic units require the creation of design space exploration techniques that can swiftly and automatically form an approximate configuration in fault-tolerant systems. Existing methods, however, use iterative design space sampling, resulting in a large amount of redundant computation. In this work, we propose the efficient FPAX automatic search framework which can learn from prior knowledge regarding the exploration process of known applications and use it to guide design exploration. This avoids excessive redundant computation and quickly provides an impressive approximate configuration. Compared with the jump search algorithm known for its efficiency, FPAX can also achieve faster convergence speed and better exploration quality. Even compared to our previous ENAP framework, it exhibits an 18 x faster performance while achieving almost identical exploration quality for several commonly used fault-tolerant applications.

关键词： Approximate computing (AC) approximate configuration design space exploration (DSE) prior knowledge

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U-SWIM: Universal Selective Write-Verify for computing-in-Memory Neural Accelerators

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第6期43卷 1822-1833页

作者： Yan, Zheyu Hu, Xiaobo Sharon Shi, Yiyu Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

Architectures that incorporate computing-in-memory (CiM) using emerging nonvolatile memory (NVM) devices have become strong contenders for deep neural network (DNN) acceleration due to their impressive energy efficiency. Yet, a significant challenge arises when using these emerging devices: they can show substantial variations during the weight-mapping process. This can severely impact DNN accuracy if not mitigated. A widely accepted remedy for imperfect weight mapping is the iterative write-verify approach, which involves verifying conductance values and adjusting devices if needed. In all existing publications, this procedure is applied to every individual device, resulting in a significant programming time overhead. In our research, we illustrate that only a small fraction of weights need this write-verify treatment for the corresponding devices and the DNN accuracy can be preserved, yielding a notable programming acceleration. Building on this, we introduce U-SWIM, a novel method based on the second derivative. It leverages a single iteration of forward and backpropagation to pinpoint the weights demanding write-verify. Through extensive tests on diverse DNN designs and datasets, U-SWIM manifests up to a 10x programming acceleration against the traditional exhaustive write-verify method, all while maintaining a similar accuracy level. Furthermore, compared to our earlier SWIM technique, U-SWIM excels, showing a 7x speedup when dealing with devices exhibiting nonuniform variations.

关键词： Artificial neural networks Programming Training Nonvolatile memory Memory management Correlation Hardware embedded systems hardware/software co-design memory noise analysis

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An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic computing Method

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IEEE transactions ON NEURAL NETWORKS AND LEARNING systems 2024年第9期35卷 12913-12923页

作者： Jia, Xiaotao Gu, Huiyi Liu, Yuhao Yang, Jianlei Wang, Xueyan Pan, Weitao Zhang, Youguang Cotofana, Sorin Zhao, Weisheng Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Beihang Hangzhou Innovat Inst Yuhang Hangzhou 310023 Peoples R China Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China Beihang Univ Sch Comp Sci & Engn BDBC Beijing 100191 Peoples R China Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands

The robustness of Bayesian neural networks (BNNs) to real-world uncertainties and incompleteness has led to their application in some safety-critical fields. However, evaluating uncertainty during BNN inference requires repeated sampling and feed-forward computing, making them challenging to deploy in low-power or embedded devices. This article proposes the use of stochastic computing (SC) to optimize the hardware performance of BNN inference in terms of energy consumption and hardware utilization. The proposed approach adopts bitstream to represent Gaussian random number and applies it in the inference phase. This allows for the omission of complex transformation computations in the central limit theorem-based Gaussian random number generating (CLT-based GRNG) method and the simplification of multipliers as and operations. Furthermore, an asynchronous parallel pipeline calculation technique is proposed in computing block to enhance operation speed. Compared with conventional binary radix-based BNN, SC-based BNN (StocBNN) realized by FPGA with 128-bit bitstream consumes much less energy consumption and hardware resources with less than 0.1% accuracy decrease when dealing with MNIST/Fashion-MNIST datasets.

关键词： Neural networks Standards Bayes methods Hardware Training Uncertainty Integrated circuit modeling Bayesian neural network (BNN) energy efficiency Gaussian random number generator stochastic computing (SC)

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