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Special Issue: "Approximation at the Edge"

ACM transactions on embedded computing systems 2023年第4期22卷 1-4页

作者： Bosio, Alberto Dolecek, Lara Kourfali, Alexandra Parameswaran, Sri Savino, Alessandro Univ Lyon CNRS Guy CollongueCPE LyonINLUMR5270 ECLINSA LyonUCBL 36 Ave Guy de Collongue F-69134 Ecully France Univ Calif Los Angeles Dept Elect & Comp Engn 7400 Boelter Hall Los Angeles CA 90095 USA Univ Stuttgart ITI Pfaffenwaldring 47 D-70569 Stuttgart Germany Univ Sydney Sch Elect Engn Bldg Sydney Australia Politecn Torino Dept Control & Comp Engn Corso Duca degli Abruzzi 24 I-10129 Turin Italy

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ATCN: Resource-efficient Processing of Time Series on Edge

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ACM transactions on embedded computing systems 2022年第5期21卷 1–19页

作者： Baharani, Mohammadreza Tabkhi, Hamed UNC Charlotte Charlotte NC 28223 USA

This article presents a scalable deep learning model called Agile Temporal Convolutional Network (ATCN) for highly accurate fast classification and time series prediction in resource-constrained embedded systems. ATCN is a family of compact networks with formalized hyperparameters that enable application-specific adjustments to be made to the model architecture. It is primarily designed for embedded edge devices with very limited performance and memory, such as wearable biomedical devices and real-time reliability monitoring systems. ATCN makes fundamental improvements over the mainstream temporal convolutional neural networks, including residual connections to increase the network depth and accuracy and the incorporation of separable depth-wise convolution to reduce the computational complexity of the model. As part of the present work, two ATCN families, namely T0 and T1, are also presented and evaluated on different ranges of embedded processors: Cortex-M7 and Cortex-A57 processors. An evaluation of the ATCN models against the best-in-class InceptionTime and MiniRocket shows that ATCN almost maintains accuracy while improving the execution time on a broad range of embedded and cyber-physical applications with demand for real-time processing on the embedded edge. At the same time, in contrast to existing solutions, ATCN is the first time series classifier based on deep learning that can be run bare-metal on embeddedmicrocontrollers (Cortex-M7) with limited computational performance and memory capacity while delivering state-of-the-art accuracy.

关键词： Temporal Convolutional Networks (TCN) Recurrent Neural Networks (RNN) real-time edge computing

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Checkpointing Models for Tasks of Different Types

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ACM transactions ON MODELING AND PERFORMANCE EVALUATION OF computing systems 2024年第3期9卷 1-23页

作者： Ezhilchelvan, Paul Mitrani, Isi Newcastle Univ Sch Comp Newcastle Upon Tyne England

A server subject to random breakdowns and repairs offers services to incoming jobs whose lengths are highly variable. A checkpointing policy is in operation, aiming to protect against possibly lengthy recovery periods by backing up the current state at periodic checkpoints. The problem of how to choose a checkpointing interval to optimise performance is addressed by analysing a general queueing model which includes breakdowns, repairs, back-ups and recoveries. Exact solutions are obtained under both Markovian and non-Markovian assumptions. Numerical experiments illustrate the conditions where checkpoints are useful and where they are not, and, in the former case, quantify the achievable benefits.

关键词： M/G/1 queue embedded Markov chains server vacations checkpoint optimisation

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A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators

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ACM transactions on embedded computing systems 2023年第4期22卷 1-31页

作者： Tsounis, Ioannis Agiakatsikas, Dimitris Psarakis, Mihalis Univ Piraeus Karaoli & Dimitriou 80 Piraeus 18534 Greece

Approximate computing Techniques (ACTs) take advantage of resilience computing applications to trade off among output precision, area, power, and performance. ACTs can lead to significant gains at affordable costswhen efficiently implemented on Field Programmable Gate Array- (FPGA) based accelerators. Although several novel ACTs works have been proposed for FPGA accelerators, their applicability to high-assurance systems has not been explored as much. ACTs are becoming necessary in many critical Edge computing systems, such as self-driving cars and Earth observation satellites, to increase computational efficiency. However, an important question comes to mind when targeting critical systems: Does ACT optimization negatively affect the reliability of the system and how can one find optimal design architectures that blend classic mitigation techniques like Triple Modular Redundancy with approximation- and precise-based arithmetic hardware units to achieve the best possible computational efficiency without compromising dependability? This work aims to solve this research problem by introducing a Design Space Exploration (DSE) methodology that employs ACTs in arithmetic units of the design and identifies Pareto-optimal microarchitectures that balance all relevant gains of ACTs, such as area, speed, power, failure rate, and precision, by inserting the correct amount of approximation in the design. In a nutshell, our DSE methodology has formulated the DSE with a Multi-Objective Optimization Problem (MOP). Each Pareto-optimal solution of our tool finds which arithmetic units of the design to implement with precise and approximate circuits and which units to selectively triplicate to remove single points of failure that compromise system reliability below acceptable thresholds. We also suggest another formulation of the DSE into a Single-Objective constraint Optimization Problem (ScOP) producing a single optimal point, and that the user may demand, as a less time-consuming

关键词： Approximate computing Techniques approximate adders FPGAs Pareto-optimal fault tolerance JPEG DCT selective-TMR

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FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第6期43卷 1650-1662页

作者： Dou, Yuqin Wang, Chenghua Waris, Haroon Woods, Roger Liu, Weiqiang Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 211106 Peoples R China Natl Univ Comp & Emerging Sci Elect Engn Dept Islamabad 44000 Pakistan Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast BT9 5AH North Ireland

Current artificial intelligence and data science applications typically require complex computations and massive amounts of data handling, presenting unprecedented challenges for embedded platforms. Approximate computing has emerged as the most promising design technique to address this issue, by providing a potential performance increase, while sacrificing accuracy within an acceptable range. Approximate arithmetic units require the creation of design space exploration techniques that can swiftly and automatically form an approximate configuration in fault-tolerant systems. Existing methods, however, use iterative design space sampling, resulting in a large amount of redundant computation. In this work, we propose the efficient FPAX automatic search framework which can learn from prior knowledge regarding the exploration process of known applications and use it to guide design exploration. This avoids excessive redundant computation and quickly provides an impressive approximate configuration. Compared with the jump search algorithm known for its efficiency, FPAX can also achieve faster convergence speed and better exploration quality. Even compared to our previous ENAP framework, it exhibits an 18 x faster performance while achieving almost identical exploration quality for several commonly used fault-tolerant applications.

关键词： Approximate computing (AC) approximate configuration design space exploration (DSE) prior knowledge

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U-SWIM: Universal Selective Write-Verify for computing-in-Memory Neural Accelerators

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第6期43卷 1822-1833页

作者： Yan, Zheyu Hu, Xiaobo Sharon Shi, Yiyu Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

Architectures that incorporate computing-in-memory (CiM) using emerging nonvolatile memory (NVM) devices have become strong contenders for deep neural network (DNN) acceleration due to their impressive energy efficiency. Yet, a significant challenge arises when using these emerging devices: they can show substantial variations during the weight-mapping process. This can severely impact DNN accuracy if not mitigated. A widely accepted remedy for imperfect weight mapping is the iterative write-verify approach, which involves verifying conductance values and adjusting devices if needed. In all existing publications, this procedure is applied to every individual device, resulting in a significant programming time overhead. In our research, we illustrate that only a small fraction of weights need this write-verify treatment for the corresponding devices and the DNN accuracy can be preserved, yielding a notable programming acceleration. Building on this, we introduce U-SWIM, a novel method based on the second derivative. It leverages a single iteration of forward and backpropagation to pinpoint the weights demanding write-verify. Through extensive tests on diverse DNN designs and datasets, U-SWIM manifests up to a 10x programming acceleration against the traditional exhaustive write-verify method, all while maintaining a similar accuracy level. Furthermore, compared to our earlier SWIM technique, U-SWIM excels, showing a 7x speedup when dealing with devices exhibiting nonuniform variations.

关键词： Artificial neural networks Programming Training Nonvolatile memory Memory management Correlation Hardware embedded systems hardware/software co-design memory noise analysis

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An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic computing Method

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IEEE transactions ON NEURAL NETWORKS AND LEARNING systems 2024年第9期35卷 12913-12923页

作者： Jia, Xiaotao Gu, Huiyi Liu, Yuhao Yang, Jianlei Wang, Xueyan Pan, Weitao Zhang, Youguang Cotofana, Sorin Zhao, Weisheng Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Beihang Hangzhou Innovat Inst Yuhang Hangzhou 310023 Peoples R China Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China Beihang Univ Sch Comp Sci & Engn BDBC Beijing 100191 Peoples R China Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands

The robustness of Bayesian neural networks (BNNs) to real-world uncertainties and incompleteness has led to their application in some safety-critical fields. However, evaluating uncertainty during BNN inference requires repeated sampling and feed-forward computing, making them challenging to deploy in low-power or embedded devices. This article proposes the use of stochastic computing (SC) to optimize the hardware performance of BNN inference in terms of energy consumption and hardware utilization. The proposed approach adopts bitstream to represent Gaussian random number and applies it in the inference phase. This allows for the omission of complex transformation computations in the central limit theorem-based Gaussian random number generating (CLT-based GRNG) method and the simplification of multipliers as and operations. Furthermore, an asynchronous parallel pipeline calculation technique is proposed in computing block to enhance operation speed. Compared with conventional binary radix-based BNN, SC-based BNN (StocBNN) realized by FPGA with 128-bit bitstream consumes much less energy consumption and hardware resources with less than 0.1% accuracy decrease when dealing with MNIST/Fashion-MNIST datasets.

关键词： Neural networks Standards Bayes methods Hardware Training Uncertainty Integrated circuit modeling Bayesian neural network (BNN) energy efficiency Gaussian random number generator stochastic computing (SC)

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InvisiGuard: Data Integrity for Microcontroller-Based Devices via Hardware-Triggered Write Monitoring

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IEEE transactions ON DEPENDABLE AND SECURE computing 2025年第1期22卷 343-358页

作者： Fang, Dongliang Peng, Anni Guan, Le van der Kouwe, Erik von Gleissenthall, Klaus Wang, Wenwen Zhang, Yuqing Sun, Limin Chinese Acad Sci Inst Informat Engn Beijing 100045 Peoples R China Univ Chinese Acad Sci Sch Cyber Secur Beijing 101408 Peoples R China Univ Chinese Acad Sci UCAS Natl Comp Network Intrus Protect Ctr Beijing 101408 Peoples R China Univ Georgia Athens GA 30602 USA Vrije Univ Amsterdam NL-1081 HV Amsterdam Netherlands

Deeply embedded devices powered by microcontrollers are widely deployed. To protect them from exploitation, many lightweight defense mechanisms, such as control flow integrity, have been proposed. However, these defenses cannot provide data integrity-a security property of particular interest in mission-critical tasks. Conversely, existing defenses that provide data integrity are too expensive to deploy in the resource-constrained context of deeply embedded devices. In this article, we propose InvisiGuard, a hardware-assisted, low overhead approach for data integrity. InvisiGuard leverages data watchpoints-a commonly available debug feature on microcontrollers-to automatically intercept write operations to critical variables. InvisiGuard then checks the legitimacy of the write instruction against an allowlist stored in a trusted execution environment (e.g., ARM TrustZone-M). By relying on the hardware to automatically intercept potentially dangerous instructions, InvisiGuard avoids heavy code instrumentation, as required by traditional solutions, making it suitable for resource-constrained microcontroller devices. We have implemented InvisiGuard on an ARM Cortex-M based development board and evaluated it with seven real-world firmware samples. Our experiments show that InvisiGuard reduces the runtime overhead by 56.99% and memory overhead by 77.37% compared with state of the art.

关键词： Monitoring Microprogramming Hardware Program processors Instruments embedded systems Data integrity Deeply embedded devices data-integrity hardware-assisted solutions

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Multi-Target-Aware Dynamic Resource Scheduling for Cloud-Fog-Edge Multi-Tier computing Network

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IEEE transactions ON INTELLIGENT TRANSPORTATION systems 2024年第5期25卷 3885-3897页

作者： Zhang, Peiying Chen, Ning Xu, Guanjun Kumar, Neeraj Barnawi, Ahmed Guizani, Mohsen Duan, Youxiang Yu, Keping China Univ Petr East China Qingdao Inst Software Coll Comp Sci & Technol Qingdao 266580 Peoples R China Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China Qilu Univ Technol Shandong Acad Sci Natl Supercomp Ctr Jinan Key Lab Comp Power Network & Informat SecurMinist Jinan 250013 Peoples R China Beijing Univ Posts & Telecommun Sch Informat & Commun Engn Beijing 100876 Peoples R China Hangzhou Dianzi Univ Space Informat Res Inst Hangzhou 310018 Peoples R China East China Normal Univ Shanghai Key Lab Multidimens Informat Proc Shanghai 200241 Peoples R China Thapar Univ Dept Comp Sci & Engn Patiala 147004 India King Abdulaziz Univ Fac Comp & Informat Technol Jeddah 21589 Saudi Arabia Mohamed Bin Zayed Univ Artificial Intelligence MBZ Machine Learning Dept Abu Dhabi U Arab Emirates Hosei Univ Grad Sch Sci & Engn Tokyo 1848584 Japan

With the maturity of 5G and Intelligent Transportation systems (ITS) technologies and the prospect of Beyond 5G (B5G) and 6G technologies, the limited lifetime and computing of mobile devices pose significant challenges to Quality of Service (QoS). In addition, the problem of inefficient use of computing, storage, communication, and other resources still exists in communication systems. In response to the above issues, Multi-tier computing Networks (MTCNs) migrate computationally intensive tasks to the cloud, fog, or edge with sufficient resources, thereby realizing energy-efficient collaborative computing and multi-dimensional resource sharing. However, in the MTCN environment with complex heterogeneity, and high-intensity dynamics, how to provide sustainable solutions for resource scheduling strategies is a meaningful issue. Inspired by Virtual Network Embedding (VNE) to decouple physical network configuration, we propose a multi-target-aware dynamic resource scheduling algorithm for MTCN to improve resource flexibility, which is the first attempt in this direction. Specifically, we consider differentiated QoS requirements like computing, storage, bandwidth, delay, etc., and establish multi-target-aware embedded constraints. Additionally, we present a Deep Reinforcement Learning (DRL)-based scheduling network that can interact scientifically and efficiently with the MTCN environment. It extracts environmental information as state input to better focus on dynamic characteristics as well as calculates candidate nodes and links using a three-layer network architecture and related constraints. Furthermore, the learning process is optimized through the combination of the reward mechanism and the gradient descent mechanism. Finally, comparison experiments on three widely used evaluation indicators (long-term average revenue, long-term average revenue-cost ratio, and VNR acceptance rate) verify that the proposed algorithm has made an average improvement of $19.042\%$ , $

关键词： Task analysis Cloud computing Quality of service Industrial Internet of Things Search problems Heuristic algorithms Dynamic scheduling Multi-tier computing networks sustainable solutions intelligent transportation systems resource scheduling virtual network embedding deep reinforcement learning

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Bit-Line computing for CNN Accelerators Co-Design in Edge AI Inference

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IEEE transactions ON EMERGING TOPICS IN computing 2023年第2期11卷 358-372页

作者： Rios, Marco Ponzina, Flavio Levisse, Alexandre Ansaloni, Giovanni Atienza, David Ecole Polytech Fed Lausanne EPFL Embedded Syst Lab CH-1015 Lausanne Switzerland

By supporting the access of multiple memory words at the same time, Bit-line computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional overhead. Such a paradigm opens novel opportunities for Artificial Intelligence (AI) at the edge, thanks to the massive parallelism inherent in memory arrays and the extreme energy efficiency of computing in-situ, hence avoiding data transfers. Previous works have shown that BC brings disruptive efficiency gains when targeting AI workloads, a key metric in the context of emerging edge AI scenarios. This manuscript builds on these findings by proposing an end-to-end framework that leverages BC-specific optimizations to enable high parallelism and aggressive compression of AI models. Our approach is supported by a novel hardware module performing real-time decoding, as well as new algorithms to enable BC-friendly model compression. Our hardware/software approach results in a 91% energy savings (for a 1% accuracy degradation constraint) regarding state-of-the-art BC computing approaches.

关键词： Edge artificial intelligence in-memory computing hardware/software co-design convolutional neural networks low-power software optimization

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