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A low-cost BIST architecture for linear histogram testing of ADCs

JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2001年第2期17卷 139-147页

作者： Azaïs, F Bernard, S Bertrand, Y Renovell, M Univ Montpellier 2 LIRMM F-34392 Montpellier 5 France

This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.

关键词： analog and mixed-signal testing ADC test Built-In Self-Test (BIST)

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Automatic tool for test set generation and DfT assessment in analog circuits

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analog INTEGRATED CIRCUITS AND signal PROCESSING 2022年第2期112卷 277-287页

作者： Zilch, Lucas B. Lubaszewski, Marcelo S. Balen, Tiago R. PGMICRO UFRGS Grad Program Microelect Porto Alegre RS Brazil

This work presents a low cost automatic test generation tool for structural analog testing. With the spice netlist and technology models of the circuit to be tested, a fault list is generated, considering a defect modeling provided by the user. The tool interacts with a spice simulator, simulating the fault-free and faulty circuits. The test development considers DC, AC (single tone) and transient (step) stimuli applied at the primary circuit inputs, computing the obtained fault coverage when taking different circuit nodes as observation points. The final test set determination relies on a fault dictionary that helps maximizing the fault coverage, at the same time as minimizing the test application. Since different circuit nodes are observed during the fault simulation campaign, this tool also helps the test developers and designers on defining Design-for-Testability strategies to increase fault detection by covering the undetected faults identified. The feasibility of the proposed method and the applicability of the tool are demonstrated with two case-studies, consisting in fully-differential integrated filters designed on a commercial 180 nm process. Results show that fault coverages near to 95% are obtained in both case-studies while requiring small test sequences with simple parametric measurements.

关键词： analog and mixed-signal testing Automatic test vector generation Fault injection Fault coverage Design-for-testability

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Defect Level Constrained Optimization of analog and Radio Frequency Specification Tests

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2015年第5-6期31卷 479-489页

作者： Sindia, Suraj Agrawal, Vishwani D. Intel Corp Hillsboro OR 97124 USA Auburn Univ ECE Dept Auburn AL 36849 USA

The objective of this work is to minimize testing cost of analog and RF circuits for which complete specification tests are available. We use an integer linear program (ILP) to eliminate as many tests as possible without exceeding the required defect level. The method leverages correlation among specifications, thereby avoiding the tests for specifications that are sufficiently covered by tests for other specifications. First, Monte Carlo simulation determines probabilities for each test covering all other specifications it was not originally intended for. These probabilities and the given defect level then define an ILP model for eliminating unnecessary tests. An hypothetical example illustration of ten specifications demonstrates that depending on the defect level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications followed by ILP optimization for two commercially available integrated circuits, an operational amplifier and a radio frequency power controller (RFPC), are presented as evidence of effectiveness of the technique.

关键词： analog and mixed-signal testing Defect-level RF testing Specification-based testing Test optimization

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Combining functional and structural approaches for switched-current circuit testing

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2000年第3期16卷 259-267页

作者： Renovell, M Azaïs, F Bodin, JC Bertrand, Y Univ Montpellier 2 LIRMM F-34392 Montpellier 5 France

This paper aims at defining an efficient test strategy for switched-current circuit testing. Taking into account the specificity of these circuits, we propose an original structural test technique as an alternative to traditionally-used Functional verification. This technique is validated both at the cell and block levels. Test results demonstrate that a high fault coverage can be achieved with a low cost test procedure. A mixed strategy combining benefits of functional and structural approaches is derived.

关键词： analog and mixed-signal testing switched-current circuits functional and structural test

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Transformer-Coupled Loopback Test for Differential mixed-signal Dynamic Specifications

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2011年第6期60卷 2014-2024页

作者： Kim, Byoungho Abraham, Jacob A. Broadcom Corp Irvine CA 92617 USA Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

Loopback tests for a differential mixed-signal device under test (DUT) have rarely been attempted since any imbalance introduced by design-for-test (DfT) circuitry on differential signaling delivers an imperfect sinusoidal wave to the DUT input or output, thereby degrading the DUT performance. In addition, this methodology inherently suffers from fault masking. These problems trigger low test accuracy and serious yield loss. This paper presents a novel methodology for the efficient prediction of individual DUT dynamic performance parameters with a radio-frequency (RF) transformer in loopback mode to overcome the imbalance of DfT circuitry and the fault masking. Cascaded RF transformers with different multiplicative weights are selected in three combinations by a multiplexer to create three separate loopback responses. These responses are used to characterize the DUT dynamic performance. Hardware measurement results show that this approach can be effectively used to predict the specifications of a DUT.

关键词： analog and mixed-signal testing built-in self-test (BIST) built-off self-test (BOST) design for test (DfT) differential signal circuit test loopback test

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BIST and production testing of ADCs using imprecise stimulus

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2003年第4期8卷 522-545页

作者： Parthasarathy, K Kuyel, T Price, D Jin, L Chen, DG Geiger, R Texas Instruments Inc Dallas TX 75266 USA Motorola Inc Tempe AZ 85284 USA Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n-bit ADC by using a ramp signal of much less than n-bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses (n+3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.

关键词： algorithms measurement analog and mixed-signal testing imprecision stimulus imprecision measurement production test built-in self-test ADC linearity

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Optimizing sinusoidal histogram test for low cost ADC BIST

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2001年第3-4期17卷 255-266页

作者： Azaïs, F Bernard, S Bertrand, Y Renovell, M Univ Montpellier 2 LIRMM F-34392 Montpellier 5 France

The histogram method is a very classical test technique for analog to Digital Converters (ADCs), but only used for external testing because of the large amount of required hardware resources. This paper discusses the viability of a BIST implementation for this technique. An original approach is developed that permits to extract the ADC parameters with a reduced area overhead. This approach involves (i) the calculation of the parameters using approximations and (ii) the decomposition of the global test in a code-after-code test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experimental data. In addition, the use of a piece-wise approximation for computing the ideal histogram also permits to minimize the memory dedicated to the storage of reference data.

关键词： analog and mixed-signal testing ADC test Built-In Self-Test (BIST)

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Efficiency of spectral-based ADC test flows to detect static errors

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2004年第3期20卷 257-267页

作者： Bernard, S Comte, M Azaïs, F Bertrand, Y Renovell, M Univ Montpellier 2 LIRMM F-34392 Montpellier 5 France

testing of analog-to-Digital Converters is classically composed of two successive and independent phases: the histogram-based test technique evaluating static specifications and the spectral analysis technique evaluating the dynamic performances. Consequently, the fundamental objective here is to investigate the feasibility of an alternative test flow involving exclusively spectral analysis to replace these two time consuming and expensive phases. The viability of this solution depends on the ability of spectral analysis to detect static specifications. In this context, this paper presents a new methodology based on a statistical approach to quantitatively evaluate the efficiency of detecting static errors from dynamic parameter measurements. This methodology has been implemented in an in-house automatic tool allowing one to process any ADC specifications. It is then possible to choose a priori the best test flow for a given application.

关键词： analog and mixed-signal testing ADC test test flow optimization

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Correlation between static and dynamic parameters of A-to-D converters:: In the view of a unique test procedure

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2004年第4期20卷 375-387页

作者： Azaïs, F Bernard, S Bertrand, Y Comte, M Renovell, M Univ Montpellier CNRS LIRMM F-34392 Montpellier 5 France

ADCs are fully characterized by both static and dynamic parameters. testing methods usually combine a histogram-based approach with a spectral analysis to determine the complete set of ADCs parameters. In the view of a unique test procedure, this paper investigates the correlation between both kinds of parameters. Experimental results demonstrate that under appropriate test conditions, the dynamic parameters extracted from a classical FFT exhibit significant variations against ADC offset, gain and non-linearity errors, opening the way of a low-cost test strategy in the frequency domain.

关键词： analog and mixed-signal testing ADC test spectral analysis

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A strategy for optimal test point insertion in analog cascaded filters

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2005年第1期21卷 9-16页

作者： Azaïs, F Lubaszewski, M Nouet, P Renovell, M Univ Montpellier CNRS LIRMM F-34059 Montpellier France UFRGS DELET Porto Alegre RS Brazil

This paper presents a strategy for synthesizing analog cascaded filters with optimal test point insertion. The strategy is based on the implementation of a selective divide-and-conquer approach that permits to ensure high fault detection capabilities while limiting DFT penalties and reducing test time. The proposed solution relies on the evaluation of the filter testability at the different inputs and outputs of the cascaded blocks in order to add DFT only when this testability is not sufficient. Efficient testability evaluation is provided through high-level fault modeling and simulation.

关键词： analog and mixed-signal testing design-for-test testability evaluation

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