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Ramp Noise Projection in cmos image sensor Single-Slope ADCs

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2017年第6期64卷 1380-1389页

作者： Levski, Deyan Waeny, Martin Choubey, Bhaskar Univ Oxford Dept Engn Sci Oxford OX1 3PJ England Awaiba Lda P-9020105 Funchal Portugal

Noise analysis of the ramp reference voltage and its projection at the output of a conventional single-slope ramp analog-to-digital converter (ADC) is presented. This paper gives insight on the reference voltage noise origins during the continuous-time ramping phase of column-parallel cmos image sensor ADCs, as well as its effect on the final ADC output noise. Theoretical modeling of an occurring random walk noise on continuous-time-based ramp references is presented first. Noise on the ramp does not directly add to the output noise of the ADC, but it is modulated and projected subject to given ramp rise time conditions. Test measurements show that the signal-dependent output noise is consistent with the rate of noise increase by the proposed random walk noise model.

关键词： cmos image sensor continuous-time integrator noise analysis ramp analog-to-digital converter (ADC) random walk noise switched-capacitor circuits Wiener process

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A cmos image sensor Based on Unified Pixel Architecture With Time-Division Multiplexing Scheme for Color and Depth image Acquisition

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2012年第11期47卷 2834-2845页

作者： Kim, Seong-Jin Kim, James D. K. Kang, Byongmin Lee, Keechang Samsung Adv Inst Technol Adv Media Lab Yongin 446712 South Korea

We propose a cmos image sensor with time-division multiplexing pixel architecture using standard pinned-photodiode for capturing 2-D color image as well as extracting 3-D depth information of a target object. The proposed pixel can alternately provide both color and depth images in each frame. Two split photodiode and four transfer gates in each pixel improve the transfer speed of generated electrons to be capable of demodulating a high-frequency time-of-flight signal. In addition, four-shared pixel architecture acquires a color image with high spatial resolution and generates a reliable depth map by inherent binning operation in charge domain. A 712 x 496 pixel array has been fabricated using a 0.11-mu m standard cmos imaging process and fully characterized. A 6-mu m pixel with 34.5% aperture ratio can be operated at 10-MHz modulation frequency with 70% demodulation contrast. We have successfully captured both images of exactly same scene from the fabricated test chip. It shows a depth uncertainty of less than 60 mm and a linearity error of about 2% between 1 and 3 m distance with 50-ms integration time. Moreover, high-gain readout operation enables to improve the performance, achieving about 43-mm depth uncertainty at 3 m.

关键词： Binning operation charge transfer speed cmos image sensor demodulation pixel depth sensor four-shared architecture high-gain readout multiresolution range finding standard pinned-photodiode three-dimensional (3-D) image sensor time-division time-of-flight (TOF)

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In-Pixel Aperture cmos image sensor for 2-D and 3-D Imaging

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IEEE sensorS JOURNAL 2018年第22期18卷 9163-9168页

作者： Choi, Byoung-Soo Kim, Sang-Hwan Lee, Jimin Seong, Donghyun Shin, Jang-Kyoo Lim, Jinyeon Chang, Seunghyuk Park, Jongho Lee, Sang-Jin Kyung, Chong-Min Kyungpook Natl Univ Sch Elect Engn Daegu 41566 South Korea Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea Korea Adv Inst Sci & Technol Ctr Integrated Smart Sensors Daejeon 34141 South Korea

This paper presents a cmos image sensor with the in-pixel aperture technique for single-chip 2-D and 3-D imaging. In conventional image sensors, the aperture is located at the camera lens. However, in the proposed image sensor, the aperture is integrated on the cmos image sensor chip and is formed at a metal layer of the cmos image sensor (CIS) process. A pixel array of the image sensor is composed of the W, R, B, and PA pixels (W pixel with integrated metal aperture) for extracting color and depth information. While the image of the W pixel becomes blurred with increasing distance from a focused object, the image of the PA pixel maintains the sharpness. Therefore, the depth image can be obtained using the depth from the defocus method. The size of the pixel, which is based on a four-transistor active pixel sensor with pinned photodiode, is 2.8 mu m x 2.8 mu m. A prototype of the proposed image sensor was fabricated using the 0.11-mu m CIS process and its performance was evaluated.

关键词： Active pixel sensor cmos image sensor pixel aperture 3D imaging

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Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated cmos image sensor Technologies

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NANO LETTERS 2017年第5期17卷 3159-3164页

作者： Horie, Yu Han, Seunghoon Lee, Jeong-Yub Kim, Jaekwan Kim, Yongsung Arbabi, Amir Shin, Changgyun Shi, Lilong Arbabi, Ehsan Kamali, Seyedeh Mahsa Lee, Hong-Seok Hwang, Sungwoo Faraon, Andrei CALTECH TJ Watson Lab Appl Phys 1200 East Calif Blvd Pasadena CA 91125 USA Samsung Elect Samsung Adv Inst Technol Suwon 443803 Gyeonggi Do South Korea Samsung Elect Adv Image Res Lab 2 North Lake Ave Pasadena CA 91101 USA

We report transmissive color filters based on subwavelength dielectric gratings that can replace conventional dye-based color filters used in backside-illuminated cmos image sensor (BSI CIS) technologies. The filters are patterned in an 80 nm-thick poly silicon film on a 115 nm-thick SiO2 spacer layer. They are optimized for operating at the primary RGB colors, exhibit peak transmittance of 6080%, and have an almost insensitive response over a +/- 20 degrees angular range. This technology enables shrinking of the pixel sizes down to near a micrometer.

关键词： Subwavelength grating high-index contrast color filters cmos image sensor

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Effect of ALD Processes on Physical and Electrical Properties of HfO2 Dielectrics for the Surface Passivation of a cmos image sensor Application

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IEEE ACCESS 2022年 10卷 68724-68730页

作者： Kim, Honggyun Chavan, Vijay D. Aziz, Jamal Ko, Byoungsu Lee, Jae-Sung Rho, Junsuk Dongale, Tukaram D. Choi, Kyeong-Keun Kim, Deok-Kee Sejong Univ Dept Elect Engn Seoul 05006 South Korea Sejong Univ Dept Elect Engn & Convergence Engn Intelligent Dr Seoul 05006 South Korea Pohang Univ Sci & Technol Dept Mech Engn Pohang 37673 Gyeongbuk South Korea Uiduk Univ Dept Renewable Energy Engn Gyeongju 38004 South Korea Shivaji Univ Sch Nanosci & Biotechnol Computat Elect & Nanosci Res Lab Kolhapur 416004 Maharashtra India Pohang Univ Sci & Technol Natl Inst Nanomat Technol Pohang 37673 Gyeongbuk South Korea

The surface passivation of a cmos image sensor (CIS) is highly beneficial for the overall improvement of a device performance. We employed the thermal atomic layer deposition (T-ALD) and plasma enhanced (PE-ALD) techniques for the deposition of 20 nm HfO2 as well as stacked with 3 and 5 nm Al2O3 thin films. The HfO2/Si and Al2O3/HfO2/Si metal-oxide-semiconductor structures were used to analyze the fixed charge density (Q(f)) and interface trap density (D-it). The as-synthesized samples show high D-it and Q(f) values (10(12) cm(-2)eV(-1)) and a minority carrier lifetime of 15-300 mu s. The finite-difference time-domain simulation of high-k dielectrics confirmed that the Al2O3 (top)/HfO2 stacked structures expected higher quantum efficiency for CIS application. The effect of vacuum annealing (VA) and forming gas annealing (FGA) treatments succeeded with the decomposition of the Dit and increase in carrier lifetime. The H-2 ambient FGA samples showed a remarkable decrease in the D-it values. To improve the overall performance of the device after passivation, we employed an Al2O3/HfO2 bilayer structure, which showed a low D-it of 10(11) cm(-2)eV(-1) and a minority carrier lifetime of similar to 3,700 mu s after 400 degrees C and 30 min FGA. We believe that this surface passivation strategy will pave way for future CIS technology regarding the development of lower defective surface and superior performance.

关键词： Atomic layer deposition carrier lifetime cmos image sensor surface passivation forming gas HfO2 interface trap density

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An approach to obtain the pinch-off voltage of 4-T pixel in cmos image sensor

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Journal of Semiconductors 2010年第7期31卷 53-56页

作者：李斌桥于俊庭徐江涛于平平 School of Electronics Information Engineering Tianjin University

An approach to obtain the pinch-off voltage of 4-T pixel in cmos image sensor is *** new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of *** results show the measured pinch-off voltage is consistent with theoretical *** technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T cmos image sensor.

关键词： pinch-off voltage cmos image sensor photon shot noise pixel design

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A dynamic range extension scheme applied to a TDI cmos image sensor

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Journal of Semiconductors 2014年第2期35卷 86-91页

作者：徐超姚素英徐江涛高志远韩立镪 School of Electronic Information Engineering Tianjin University

A dynamic range extension scheme applied to a time delay integration （TDI） cmos image sensor （CIS） is presented. Two types of pixels with higher and lower conversion gain are adopted in the pixel array, which are suitable for capturing images in low and high illumination respectively. By fusing the two kinds of pixels＇ output signals in the process of TDI accumulation, a high dynamic range image can be achieved. Compared with the traditional multiple integration technique, no photoelectrons generated during the exposure time are discarded by the reset operation, and thus a higher level of signal-to-noise ratio （SNR） can be retained. A prototype chip with an 8 × 8 pixel array is implemented in a 0.18 μm CIS process, and the pixel size is 15 × 15 μm2. Test results show that a 76 dB dynamic range can be achieved in 8-stage TDI mode, when the SNR boost can reach 7.26 dB at 90.8 lux.

关键词： cmos image sensor time delay integration dynamic range extension digital domain

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An On-Chip Binary-Weight Convolution cmos image sensor for Neural Networks

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2021年第8期68卷 7567-7576页

作者： Kim, Woo-Tae Lee, Hyunkeun Kim, Jung-Gyun Lee, Byung-Geun Gwangju Inst Sci & Technol Sch Elect Engn & Comp Sci Gwangju 61005 South Korea

A cmos image sensor (CIS) that can perform on-chip binary convolution is presented. The CIS can greatly reduce memory usage and computational complexity by directly generating a feature map for a binary neural network. The pixel readout of the CIS is performed in the column-parallel fashion using incremental delta-sigma analog-to-digital converters (ADCs). The CIS operates in two different modes: convolution and normal modes. When the column ADC is working in the convolution mode, it works as a first-order delta-sigma ADC and generates convolved images using a binary kernel. In the normal operation mode, the ADC is switched to a second-order delta-sigma ADC with little hardware modification and used to capture high-quality images. To demonstrate the CIS architecture, a 192 x 128-pixel CIS, which occupies an active die area of 14.44 mm(2), is fabricated in a 0.18 mu m standard cmos process. The performance of the CIS is evaluated through measurements and network simulations. In the normal operation mode, the CIS achieves a read noise of 14.79 e(rms)(-) and a full-well capacity of 6,420 e(-) with a resulting dynamic range of 53 dB. The power consumptions of the CIS are 49.2 and 52.5 mW during the normal and convolution modes, respectively.

关键词： Kernel Convolution Quantization (signal) Modulation Neural networks Field programmable gate arrays Application specific integrated circuits Binary weight neural network cmos image sensor convolution operation incremental delta-sigma analog-to-digital converter

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A time-to-first spike cmos image sensor with coarse temporal sampling

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2006年第3期47卷 303-313页

作者： Luo, Q Harris, JG Chen, ZLJ Marvell Semicond Inc Sunnyvale CA USA

Conventional voltage-based cmos image sensors inherently have a dynamic range of about 60 dB. To extend the dynamic range, a two-degree of freedom time-based cmos image sensor is proposed. Instead of reading analog voltages off chip, a time representation is used to record when the photodetector voltage passes a timing-varying threshold. The time measurements are combined with the reference voltage waveform to reconstruct the image. Experimental results on a prototype 32 x 32 pixel array cmos image sensor verify that the two-degree of freedom sampling technique is feasible for ultra-wide dynamic range imaging. A measured 115 dB dynamic range at 30 fps is obtained.

关键词： cmos image sensor dynamic range time-based sampling

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A Linear-Logarithmic cmos image sensor With Adjustable Dynamic Range

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IEEE sensorS JOURNAL 2016年第13期16卷 5222-5226页

作者： Bae, Myunghan Choi, Byoung-Soo Jo, Sung-Hyun Lee, Hee-Ho Choi, Pyung Shin, Jang-Kyoo Kyungpook Natl Univ Sch Elect Engn Coll IT Engn Taegu 702701 South Korea

A new pixel structure is proposed for wide dynamic range cmos image sensors. A pixel based on a three-transistor active pixel sensor has two linear responses and a logarithmic response using additional circuits. The photogate surrounding the n(+)/p-sub photodiode exists for the second linear response. The logarithmic response is due to the biased MOS cascode. The proposed pixel was designed and fabricated using a 0.35-mu m 2-poly 4-metal standard cmos process. The dynamic range of the pixel is higher than 106 dB. A test chip with a pixel pitch of 10 x 10 mu m(2) and a 160 x 120 pixel array is evaluated.

关键词： cmos image sensor dynamic range linear-logarithmic response photogate

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