检索结果-内蒙古大学图书馆

IEEE OPEN JOURNAL OF NANOTECHNOLOGY 2022年 3卷 85-93页

作者： Dikshit, Surya Narain Nisar, Arshid Dhull, Seema Bindal, Namita Kaushik, Brajesh Kumar Indian Inst Technol Roorkee Dept Elect & Commun Engn Roorkee 247667 Uttar Pradesh India

Spintronics is one of the emerging fields for next-generation low power, high endurance, non-volatile, and area efficient memory technology. Spin torque transfer (STT), spin orbit torque (SOT), and electric field assisted switching mechanisms have been used to switch magnetization in various spintronic devices. However, their operation speed is fundamentally limited by the spin precession time that typically ranges in 10-400 ps. Such a time constraint severely limits the possible operation of these devices in high-speed systems. Optical switching using ultrashort laser pulses, on the other hand, is able to achieve sub-picosecond switching operation in magnetic tunnel junctions (MTJs). In this paper, all optically switched (AOS) MTJ has been used to design high speed and low power hybrid MTJ/cmos based logic circuits such as AND/NAND, XOR/XNOR, and full adder. Owing to the ultra-fast switching operation of AOS-MTJ, the circuit level results show that the energy and speed of AOS-MTJ based logic circuits are improved by 85% and 97%, respectively, when compared to STT based circuits. In comparison to SOT based designs, the proposed logic circuits show 10% and 91% improvement in energy efficiency and speed, respectively.

关键词： Magnetic tunneling Optical switches Magnetization Vertical cavity surface emitting lasers logic circuits Lattices Integrated circuit modeling All-optical-switching magnetic tunnel junction MTJ cmos logic circuits spintronics

来源：评论

学校读者我要写书评

暂无评论

Air-stable N-type printed carbon nanotube thin film transistors for cmos logic circuits

引用

CARBON 2020年 163卷 145-153页

作者： Wei, Miaomiao Robin, Malo Portilla, Luis Ren, Yunfei Shao, Shuangshuang Bai, Lan Cao, Yu Pecunia, Vincenzo Cui, Zheng Zhao, Jianwen Univ Sci & Technol China Sch Nanotech & Nanobion SEID 398 Ruoshui RdSuzhou Ind Pk Suzhou 215123 Jiangsu Peoples R China Chinese Acad Sci Printable Elect Res Ctr Suzhou Inst Nanotech & Nanobion SEID 398 Ruoshui RdSuzhou Ind Pk Suzhou 215123 Jiangsu Peoples R China Soochow Univ Inst Funct Nano & Soft Mat FUNSOM Jiangsu Key Lab Carbon Based Funct Mat & Devices Joint Int Res Lab Carbon Based Funct Mat & Device 199 Renai Rd Suzhou 215123 Jiangsu Peoples R China Chinese Acad Sci Technol & Engn Ctr Space Utilizat Key Lab Space Utilizat 9 Deng Zhuang South Rd Beijing 100094 Peoples R China

The lack of long-term air-stable and solution-processed n-doping methods for printed single-walled carbon nanotube (SWCNT) thin film transistors (TFTs) limits their integrations into printed complementary metal-oxide-semiconductor (cmos) circuits. In this paper, a new chemically modified epoxy amine ink was developed as the chemical dopant and encapsulant to enable the uniform n-type SWCNT-TFTs with long-term air stability (6 months). The epoxy amine inks were dropped onto the printed p-type TFT device channels in a single-step solution process. As a result, printed top-contact n-type SWCNT-TFTs were obtained with well-balanced electrical chararcteristics comparable to their p-type counterparts. The matched p-type and n-type SWCNT-TFTs were thus integrated into the printed cmos inverters and NAND gates, which have both achieved proper logic operation at supply voltages below 1 V. In particular, the cmos inverters could operate with VDD down to 0.3V with associated peak power consumption of 0.06 mu W, showing full rail-to-rail output swings with voltage gains up to 22, trip voltages of -V-DD/2, and maximum noise margin of 0.42 Vat V-DD = 1.1 V (-76.4% of V-DD/2). Furthermore, the static characteristics of cmos inverters could be maintained for 3 months with negligible changes, proving the feasibility of this long-term air-stable n-doping method. (C) 2020 Elsevier Ltd. All rights reserved.

关键词： Semiconducting single-walled carbon nanotubes (sc-SWCNTs) Printed thin film transistors (TFTs) N-doped Epoxy resin Air stability cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

Optimum transistor sizing of cmos logic circuits using logical effort theory and evolutionary algorithms

引用

INTEGRATION-THE VLSI JOURNAL 2018年第Jan.期60卷 25-38页

作者： Singh, Kunwar Jain, Aman Mittal, Aviral Yadav, Vinay Singh, Atul Anshuman Jain, Anmoll Kumar Gupta, Maneesha Netaji Subhas Inst Technol New Delhi India

Most existing methodologies use either logical Effort (LE) theory or stand-alone optimization algorithms for automated transistor sizing of cmos logic circuits. LE theory optimizes a logic circuit only with respect to speed while it completely ignores power and area. Whereas heuristic algorithms when used as a stand-alone approach for optimization lead to huge computational effort since there is no predefined technique to apply constraints on transistor sizes in order to limit the design space for target specifications. The problem has been resolved in this paper by utilizing delay sensitivity factor based on LE theory proposed by Alioto et. al. [1] for estimating the highest operating speed of a logic circuit and determining the upper bound on the size of transistors. Recently proposed heuristic algorithms viz. Interior Search Algorithm (ISA) [2] and Gravitational Search Algorithm (GSA) [3] have been utilized further to converge towards minimum power-delay-area product (PDAP). Simulation results for various test circuits indicate upto 35.1% and 63.8% improvement in power-delay product (PDP) and PDAP respectively in 130 nm/1.2 V TSMC cmos technology. PVT analysis and Monte Carlo simulations have been used to further validate the effectiveness of the proposed methodology.

关键词： Digital VLSI cmos logic circuits Optimization logical effort theory Heuristic algorithms Power-delay-area product

来源：评论

学校读者我要写书评

暂无评论

A Sense-Amplifier Flip-Flop With Transition Completion Detection Scheme in 16nm for Low-Voltage and Low-Area Applications

引用

ELECTRONICS LETTERS 2025年第1期61卷

作者： Lin, Jin-Fa Yang, Cheng-Hsueh Chaoyang Univ Technol Dept Informat & Commun Engn Taichung Taiwan

A low-power sense-amplifier (SA) flip-flop (FF) with transition completion detection is proposed for low-voltage applications. By replacing logic functions, the proposed detection circuit can be efficiently integrated into SA and latch designs, leading to a significant reduction in area while reducing power and ensuring reliable operation at low voltage. The post-layout simulation results implemented in the TSMC 16-nm cmos process show that, at an operating voltage of 0.4 V and a switching activity of 25%, the proposed design achieves a 25.8% reduction in power and up to 38.7% area savings compared to previous designs.

关键词： cmos digital integrated circuits cmos logic circuits VLSI

来源：评论

学校读者我要写书评

暂无评论

HiCTL: High Fan-in Differential Capacitive-Threshold-logic Gate Implementation With an Offset-Compensated Comparator 25

HiCTL: High Fan-in Differential Capacitive-Threshold-Logic G...

引用

25th International Symposium on Quality Electronic Design (ISQED)

作者： Sahruri, Abdullah Margala, Martin Cilingiroglu, Ugur Univ Louisiana Lafayette Sch Comp & Informat Lafayette LA 70504 USA Yeditepe Univ Elect & Elect Engn Istanbul Turkiye

ISBN: (纸本)9798350309270;9798350309287

Computing applications now require highly dense, fast, and complex Boolean computations for bulk bitwise operations. This paper aims to introduce a new threshold logic gate that utilizes a high fan-in with a compact area and low propagation delay. Due to its high fan-in capability and low delay, the threshold logic gate is well-suited for applications demanding fast data-intensive computations. What usually limits fan-in in threshold-logic gates is the offset of the comparator by which the output signal is digitized. The comparator utilized in this work reduces its offset in a very compact area by utilizing a purely capacitive feedback loop. The gate performs sum-of-product and thresholding operations by setting the minimum-sized MOSFET capacitors individually. This is achieved by setting the threshold and input voltages with digital logic levels. The gate operation is dynamic and comprises two phases, in which the inputs and threshold setting are done during the reset phase while the comparator provides the resultant at the evaluation phase. The analysis, properties, and limitations of implementing a high fan-in threshold logic gate are presented by analyzing five gates of fanins 31, 63, 127, 255, and 511, along with a post-layout analysis of the 511 fan-in gate. The gate's design was validated using 65nm cmos technology.

关键词： Threshold logic gate logic design cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

Highly Stable Oxide Thin-Film Transistor-Based Complementary logic circuits under X-ray Irradiation

引用

ACS APPLIED ELECTRONIC MATERIALS 2022年第7期4卷 3606-3614页

作者： Yatsu, Kie Lee, Hyun-Ah Kim, Dae Hwan Park, Ick-Joon Kwon, Hyuck-In Joongbu Univ Dept Elect & Elect Engn Goyang 10279 South Korea Chung Ang Univ Sch Elect & Elect Engn Seoul 06974 South Korea

A radiation-hard oxide-thin-film transistor (TFT)-based complementary metal-oxide-semiconductor (cmos) logic circuit composed of p-type tin oxide (SnOX) and n-type indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) was proposed. The chemical states and crystalline structure of oxide thin films and their surface morphologies were analyzed as a function of the X-ray irradiation dose, exhibiting excellent radiation stability and durability for both oxide thin films under X-ray irradiation. After X-ray irradiation at a very high dose, a slight change in the chemical states was observed in both thin films, that is, an increase in the oxygen vacancies and tin dioxide components in the SnOX thin films and in the oxygen vacancy components in the IGZO thin films. The change in the chemical states observed in both thin films after X-ray irradiation explained the slight X-ray-induced negative shift of the transfer curves for both oxide TFTs. The fabricated cmos inverter exhibited typical voltage transfer characteristics and a maximum gain of & SIM;33.4 V/V at a supply voltage of 10 V, which were well sustained after X-ray irradiation, even at a high dose of 100 Gy. In this study, we show that oxide-TFT-based cmos logic circuits can potentially be used to demonstrate high-performance and radiation-robust large-area electronic systems operating in harsh X-ray environments.

关键词： X-ray irradiation radiation robustness SnOX TFT IGZO TFT cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

TVD-PB logic circuit based on camouflaging circuit for IoT security

引用

IET circuits DEVICES & SYSTEMS 2022年第1期16卷 40-52页

作者： Zhang, Yuejun Wu, Qiufeng Wang, Pengjun Wen, Liang Luan, Zhicun Gu, Chongyan Ningbo Univ Fac Elect Engn & Comp Sci Ningbo Zhejiang Peoples R China Wenzhou Univ Coll Elect & Elect Engn Wenzhou 325035 Peoples R China China Coast Guard Acad Dept Elect Technol Ningbo Zhejiang Peoples R China Queens Univ Belfast Inst Elect Commun & Informat Technol Ctr Secure Informat Technol Belfast Antrim North Ireland

Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side-channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage-defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull-down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. As a result, the power consumption of the circuit attains balance and stability between two different logical operations. The proposed threshold voltage-defined power-balance (TVD-PB) design is fabricated using a 65-nm cmos technology, and the core area occupies approximately 0.0044 mm(2), composed of NAND, NOR, XOR, and INV components and multiplier gates of the proposed TVD-PB circuit. The entire chip passed the logic function tests. The measured results show that the average similarity of the TVD-PB universal gate is 99.68%. In addition, the current margin is higher than 55 mu A and power consumption of 0.455 mW during each clock cycle at 1.2 V derives 0.1072% of the normalized energy deviation and 0.0453% of the normalized standard deviation. Compared with other state-of-the-art techniques, the power dependency against power attacks is improved effectively.

关键词： Internet of Things devices power attacks logic gates IoT devices logic functions physical attacks logic camouflaging circuit threshold voltage-defined technique IoT security power 0.455 mW TVD-PB logic circuit size 65 nm threshold voltage-defined power-balance symmetric differential pull-down network TVD-PB universal gate logic design side-channel analysis threshold voltage reconfiguration circuit security threshold logic Internet of Things integrated circuit design antiphysical attack scheme power consumption logical operations voltage 1.2 V circuit stability TVD-PB design reverse engineering hardware security power dependency circuit balance cmos logic circuits logic function tests

来源：评论

学校读者我要写书评

暂无评论

Characterizing a standard cell library for large scale design of memristive based signal processing

引用

IET circuits DEVICES & SYSTEMS 2022年第1期16卷 13-25页

作者： Sasi, Abubaker Ahmadi, Arash Ahmadi, Majid Univ Windsor Dept Elect & Comp Engn Windsor ON N9B 3P4 Canada

In recent years, the use of memristors in circuits design has rapidly increased and attracted research interest. Advances have been made to both the size and the complexity of memristor designs. Therefore, computer aided design tools are required to handle memristor-based large-scale designs. A comprehensive automatic framework for the design and synthesis of large-scale memristor-complementary metal-oxide-semiconductor (cmos) circuits is described herein. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library file for large-scale simulation. The proposed architecture is based on RRAM and ReRAM redox-based devices and the memristor ratioed logic design approach. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was verified with Verilog-XL, MATLAB, and the electronic design automation synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. Nevertheless, it is perfectly suitable for signal processing applications that require MATLAB functions to produce text files with hex values in order to overcome the limitations of the simulation environment. A framework is deployed herein for design of the memristor-based parallel 8-bit adder/subtractor and a 2D memristive-based median filter. Both proposed designs memristor-based adder/subtractor and memristive median filter have significant power reductions of 66% and 16% respectively, when compared to the same designs using cmos technology.

关键词： median filters computer aided design tools logic gates digital logic design circuits design low-power electronics large-scale memristor-complementary metal-oxide-semiconductor circuits electronic design automation synopses compiler memristor designs adders comprehensive automatic framework 2D memristive-based median filter memristive based signal processing standard cell library file memristor-based digital logic designs RRAM memristors hardware description languages logic design approach electronic design automation signal processing applications large-scale simulation MATLAB logic design characterization methodology cmos technology cmos integrated circuits large-scale designs integrated circuit design ReRAM redox-based devices memristor-based logic cells Cadence Virtuoso schematic-level environment cmos logic circuits Verilog-XL

来源：评论

学校读者我要写书评

暂无评论

Challenges to adopting adiabatic circuits for systems-on-a-chip

引用

IET circuits DEVICES & SYSTEMS 2021年第6期15卷 581-593页

作者： Rengarajan, Krishnan S. Mondal, Saroj Kapre, Ravindra BITS Pilani EEE Dept Hyderabad Campus Hyderabad India Infineon Technol Amer IFAM San Jose CA USA

Adiabatic complementary metal-oxide-semiconductor (cmos) circuits have been proposed as a low-power option for cmos systems-on-a-chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow-transitioning clock phases demands the generation and distribution of clock phases precisely and efficiently. This power must be more than offset by the power saved by using adiabatic circuits. The problems in adiabatic logic circuits are described, and solutions are proposed to address them. Three published topologies are considered, namely positive-feedback adiabatic logic (PFAL), two-level adiabatic logic (2-LAL) and clocked adiabatic logic in 40 nm cmos technology at 100 MHz. New circuit ideas for complete level restore in PFAL and avoidance of floating nodes in 2-LAL are presented. The problem with 2-LAL multi-input gates is published and solved for the first time here using a modified PFAL. The conclusion is that a 3X power savings in PFAL is about the best that can be achieved in an SoC context-a low return given the required investments in area and complexity. This should motivate the future discovery of more efficient solutions.

关键词： two-level adiabatic logic low-power electronics SoC context 2-LAL multiinput gates new circuit ideas system-on-chip frequency 100.0 MHz cmos systems-on-a-chip logic design low-power option cmos technology cmos circuits adiabatic complementary metal-oxide-semiconductor circuits PFAL clocks positive-feedback adiabatic logic size 40.0 nm slow-transitioning clock phases adiabatic logic circuits cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm cmos technology

引用

IET circuits DEVICES & SYSTEMS 2021年第6期15卷 571-580页

作者： Kumar, Sabavat Satheesh Sundaram, Kumaravel Padmanaban, Sanjeevikumar Holm-Nielsen, Jens Bo Blaabjerg, Frede Vellore Inst Technol Sch Elect Engn Vellore Tamil Nadu India Aalborg Univ Ctr Bioenergy & Green Engn Dept Energy Technol Niels Bohrs Vej 8 DK-6700 Esbjerg Denmark Aalborg Univ Ctr Reliable Power Elect Dept Energy Technol Aalborg Denmark

Conventional flip-flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation-hardened flip-flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard-gated Quatro cell, and so on, are discussed. The flip-flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip-flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard-gated Quatro FF (GQFF) using guard-gated Quatro cell and Muller C-element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual-input Muller C-element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (cmos) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.

关键词： radiation-hardened flip-flops dual interlocked cell SEU inverter stages flip-flops single node upset dual-input Muller C-element IVQFF low-power electronics guard-gated Quatro FF using guard-gated Quatro cell GQFF output stage triple modular redundancy size 45.0 nm Complementary Metal Oxide Semiconductor technology soft error resilience guard-gated Quartro-based flip-flop single event upset invertors logic design Quatro cell cmos technology radiation hardening (electronics) radiation environment cmos logic circuits Quatro flip-flop

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：