检索结果-内蒙古大学图书馆

Low-power successive approximation ADC using split-monotonic capacitive DAC

IET circuits DEVICES & SYSTEMS 2018年第2期12卷 203-208页

作者： Shakibaee, Fatemeh Sajedi, Fereshteh Saberi, Mehdi Ferdowsi Univ Mashhad Dept Elect Engn Mashhad *** Iran

A power-efficient successive approximation analogue-to-digital converter (SA-ADC) is proposed. In order to reduce the energy consumption of the employed capacitive digital-to-analogue converter (DAC), a new low-energy capacitor switching technique is proposed which consumes no switching energy during the first three comparison steps. Moreover, an energy-efficient split-monotonic technique is utilised for the rest of the operations. Compared with the capacitor switching technique used in the conventional SA-ADC, the proposed scheme not only reduces the switching energy by 99.23% but also it has lowered the total capacitor size by 75%. Furthermore, in order to realise the proposed capacitor switching scheme, a power-efficient logic circuit is designed which reduces the power consumption of the required control logic circuit by reducing the activity of the employed D-type flip-flops. Based on the proposed scheme, a 10 bit 40kS/s SA-ADC has been designed and simulated in a 0.18 mu m complementary metal-oxide semiconductor technology with a supply voltage of 1V. Post-layout simulation results show that the proposed ADC circuit achieves a signal-to-noise-and-distortion ratio of 60.8dB at the cost of 270nW power consumption, resulting in a figure-of-merit of 7.6fJ/conversion step.

关键词： low-power electronics analogue-digital conversion digital-analogue conversion capacitor switching cmos logic circuits logic design flip-flops integrated circuit layout power 270 nW noise figure 60 8 dB voltage 1 V size 0 18 mum word length 10 bit signal-to-noise-and-distortion ratio post-layout simulation cmos technology D-type flip-flop control logic circuit power consumption power efficient logic circuit design low-energy capacitor switching technique DAC energy consumption SA-ADC low power-efficient successive approximation analogue-to-digital converter energy efficient split-monotonic capacitive digital-to-analogue converter

来源：评论

学校读者我要写书评

暂无评论

16-bit 1-MS/s SAR ADC with foreground digital-domain calibration

引用

IET circuits DEVICES & SYSTEMS 2018年第4期12卷 505-513页

作者： Guan, Rui Xue, Jianfeng Yang, Chao Jin, Jing Zhou, Jianjun Shanghai Jiao Tong Univ 800 Dongchuan Rd Shanghai 200240 Peoples R China

This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and segment error' of split-CDAC array is proposed. The split-CDAC architecture combines a V-cm-free technique in a floating CDAC scheme. The V-cm-free technique avoids a power hungry V-cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 mu m 1P6M Complementary Metal Oxide Semiconductor (cmos) technology, and achieves 86.16dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41pJ/conversion-step.

关键词： analogue-digital conversion calibration low-power electronics biomedical equipment cmos logic circuits SAR ADC low-power successive approximation register analogue-to-digital converter medical instrument applications foreground digital-domain calibration method mismatch error correction capacitive digital-to-analogue converter split-CDAC array architecture V-cm-free technique floating CDAC scheme power hungry V-cm generator modified direct-switching SAR logic 1P6M cmos technology signal-to-noise and distortion ratio word length 16 bit size 0 18 mum noise figure 86 16 dB

来源：评论

学校读者我要写书评

暂无评论

65-nm cmos low-energy RNS modular multiplier for elliptic-curve cryptography

引用

IET COMPUTERS AND DIGITAL TECHNIQUES 2018年第2期12卷 62-67页

作者： Asif, Shahzad Andersson, Oskar Rodrigues, Joachim Kong, Yinan Macquarie Univ Dept Engn Sydney NSW Australia Lund Univ Dept Elect & Informat Technol Lund Sweden

Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest-Shamir-Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40-channel RNS moduli-set is proposed for this architecture to benefit from the short-channel width of the RNS moduli-set. The throughput of the architecture is enhanced by pipelining and pre-computations. The proposed architecture is fabricated as an ASIC using 65-nm cmos technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25V. The maximum throughput of the proposed design is 1037Mbps while operating at a frequency of 162MHz with an energy dissipation of 48nJ. The proposed architecture enables the construction of low-voltage and energy-efficient ECCs.

关键词： public key cryptography residue number systems multiplying circuits cmos logic circuits 65-nm cmos low-energy RNS modular multiplier elliptic-curve cryptography algorithm modular multiplication Rivest-Shamir-Adleman cryptography algorithm elliptic curve point multiplication modular exponentiation Chinese remainder theorem residue number system 40-channel RNS moduli-set short-channel width ASIC energy dissipation low-voltage ECC energy-efficient ECC

来源：评论

学校读者我要写书评

暂无评论

Power optimisation of both a high-speed counter and a retiming element for 2.4 GHz digital PLLs

引用

ELECTRONICS LETTERS 2018年第5期54卷 284-285页

作者： Silva-Pereira, M. Caldinhas Vaz, J. ULisboa Inst Super Tecn Inst Telecomunicacoes Lisbon Portugal

The power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 m cmos technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 W when operating with a 2.4 GHz input signal.

关键词： counting circuits digital phase locked loops low-power electronics flip-flops cmos logic circuits UHF integrated circuits power optimisation high-speed counter retiming element digital PLL ultralow-power digital phase-locked-loops ultralow-power PLL asynchronous topology sampling phase generator custom true single-phase clock logic style TSPC logic style TSPC flip-flop optimal power efficiency cmos technology frequency 2 4 GHz size 0 13 mum

来源：评论

学校读者我要写书评

暂无评论

Calibration method to reduce the error in logarithmic conversion with its circuit implementation

引用

IET circuits DEVICES & SYSTEMS 2018年第4期12卷 301-308页

作者： Zhao, Zhou Srivastava, Ashok Peng, Lu Mohanty, Saraju P. Louisiana State Univ Div Elect & Comp Engn Baton Rouge LA 70803 USA Univ North Texas Dept Comp Sci & Engn Denton TX USA

Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180nm cmos. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709mW, and the delay is 1.82ns under operational DCVLS.

关键词： calibration binary codes clocks cmos logic circuits calibration method circuit implementation Mitchell's logarithmic conversion fast calibration method fixed binary code conversion error highly paralleled circuit differential cascade voltage switch logic high-speed logic adiabatic logic power dissipation low-cost adiabatic clock generator passive component four-phase sine clock logarithmic converter cmos word length 8 bit size 180 nm power 1 12 mW power 3 709 mW time 1 82 ns

来源：评论

学校读者我要写书评

暂无评论

Low-noise dynamic comparator circuit with selectable input-referred thermal noise voltage

引用

ELECTRONICS LETTERS 2018年第21期54卷 1210-1211页

作者： Yazid, M. Inst Teknol Sepuluh Nopember Dept Biomed Engn Surabaya Indonesia

A new method for reducing input-referred thermal noise of dynamic comparator circuit without increasing load capacitance as commonly used in the conventional method is proposed. An implementation circuit with selectable low-noise mode operation is presented, which enable both low-noise mode and standard mode operation by a single circuit. Simulation in 180 nm cmos process technology shows that the proposed new method and circuit topology can achieve up to 90% increase in gain of comparator first stage, resulting in up to 40% decrease in input-referred thermal noise voltage, compared with a conventional circuit with similar load capacitance. The proposed circuit is also able to operate with similar performance as the conventional circuit when low-noise mode operation is not necessary.

关键词： comparators (circuits) thermal noise flip-flops cmos logic circuits logic design low-noise mode operation circuit topology comparator first stage low-noise dynamic comparator circuit cmos process technology load capacitance input-referred thermal noise voltage

来源：评论

学校读者我要写书评

暂无评论

Reliability and performance of optimised Schmitt trigger gates

引用

JOURNAL OF ENGINEERING-JOE 2018年第8期2018卷 735-744页

作者： Tache, Mihai Ibrahim, Walid Kharbash, Fekri Beiu, Valeriu Aurel Vlaicu Univ Arad Fac Exact Sci Dept Math & Comp Sci Arad Romania Univ Politehn Bucuresti Bucharest Romania United Arab Emirates Univ Coll Informat Technol Dept Comp & Network Engn Al Ain U Arab Emirates

This study compares the performance and reliability of classical complementary metal-oxide-semiconductor (cmos) gates with Schmitt trigger (ST) ones. The ST hysteresis, caused by the added positive feedback transistors, improves the design static noise margin (SNM) and offers noise immune operation. Hence, ST-based circuits are expected to operate more reliably than the ones implemented using classical cmos. Although many research papers have been focused lately on using ST design concepts for implementing more reliable static random access memory (SRAM) cells, significantly less work was devoted to the application of ST concepts in the combinatorial logic domain. Moreover, available research on ST-based logic gates had only focused on the low-voltage/power applications range. The authors are going to look at the whole voltage range and performance spectrum to compare and understand not only the SNMs and the power consumption (at different frequencies and voltage levels) but also the delay and the power-delay-product of ST-based logic gates. These will be compared with classical cmos as well as with optimally sized cmos and ST-based logic gates. This study should give a clear picture of the potential advantages ST could offer for combinatorial logic in advanced cmos technology nodes and of their application range.

关键词： trigger circuits integrated circuit reliability logic gates SRAM chips low-power electronics cmos logic circuits integrated circuit design logic design performance spectrum ST-based logic gates optimised Schmitt trigger gates reliability classical complementary metal-oxide-semiconductor gates ST hysteresis design static noise margin noise stable operation ST-based circuits ST design concepts reliable SRAM cells low-voltage-power applications classical cmos gates positive feedback transistors combinatorial logic domain power consumption power-delay-product advanced cmos technology nodes

来源：评论

学校读者我要写书评

暂无评论

Dual-edge triggered JK flip-flop with comprehensive analysis in quantum-dot cellular automata

引用

JOURNAL OF ENGINEERING-JOE 2018年第7期2018卷 354-359页

作者： Zhang, Yongqiang Xie, Guangjun Lv, Hongjun Hefei Univ Technol Sch Elect Sci & Appl Phys Hefei 230009 Anhui Peoples R China

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective substitution of conventional complementary metal oxide semiconductor (cmos)-based integrated circuits. A new dual-edge triggered JK flip-flop based on a novel dual-edge triggered structure with less fundamental building gates is proposed in QCA domain in this study. To get a more robust triggered structure, the probabilistic transfer matrix is employed to analyse the reliability of the structure. The functionalities of the dual-edge triggered structure and JK flip-flop are verified with QCADesigner, a simulation tool widely used. By arranging the clock zones serially and QCA cells logically, compared with previous circuits, both of the proposed triggered structure and JK flip-flop perform well in terms of cells count, area, complexity, QCA cost and power dissipation at different tunnelling energy levels at 2 K temperature, respectively.

关键词： flip-flops quantum dots cellular automata nanoelectronics logic design cmos logic circuits probability matrix algebra logic gates quantum-dot cellular automata integrated circuits fundamental building gates QCA domain robust triggered structure probabilistic transfer matrix QCA cells power dissipation dual-edge triggered JK flip-flop cmos-based integrated circuits dual-edge triggered structure structure reliability analysis QCADesigner simulation tool clock zones temperature 2 0 K

来源：评论

学校读者我要写书评

暂无评论

Circuit Analysis of Pass Transistors and Inverter based on Negative Capacitance Silicon-Germanium Double Gate FET (NCSiGeDGFET)

Circuit Analysis of Pass Transistors and Inverter based on N...

引用

Global Conference for Advancement in Technology (GCAT)

作者： Monika Bansal Harsupreet Kaur Department of Electronic Science University of Delhi Delhi India

ISBN: (纸本)9781728136950

This work presents the performance of Negative Capacitance Silicon-Germanium Double Gate FET (NCSiGeDGFET) based pass transistors and inverter. The ferroelectric layer has been introduced to reduce the power dissipation while SiGe has been incorporated to improve the current drivability. The static and transient characteristics of NCpMOS-Pass Transistor (NCpMOS-PT), NCnMOS-Pass Transistor (NCnMOS-PT), and NCcmos inverter have been obtained by solving Landau-Khalatnikov equation with TCAD 2D electrostatic. It has been shown that NCpMOS-PT, NCnMOS-PT, and NCcmos exhibit superior performance in terms of steeper characteristics and reduced static and switching power dissipation as compared to conventional pass transistors and inverter.

关键词： cmos logic circuits ferroelectric materials Ge-Si alloys logic gates technology CAD (electronics) Transistor Device Component Germanium silicon alloys cmos logic circuits Inventors Ferroelectric materials logic gates Circuit analysis Silicon germanium Power dissipation Transient performance capacitance Capacitors

来源：评论

学校读者我要写书评

暂无评论

Study on Temperature Stability and Fault Tolerance of Adder in Quantum-dot Cellular Automata

Study on Temperature Stability and Fault Tolerance of Adder ...

引用

IEEE International Conference on Signal Processing, Computing and Control (ISPCC)

作者： Jayanta Pal Shiboprosad Bhattacharjee Apu Kumar Saha Paramartha Dutta Tripura University Suryamaninagar Tripura India Tripura University Suryamaninagar India NIT Agartala West Tripura India Visva-Bharati University West Bengal India

ISBN: (纸本)9781728139890

Quantum-dot Cellular Automata (QCA) is the most sought after paradigms for designing layouts for digital circuits on a Nano-Scale. It has an edge over cmos as the designs in QCA consume less power, are very small and their execution is very fast. QCA can perform computations which are dense in nature. It is being considered as a cmos VLSI alternate. The cells in QCA transfer data based on their polarization state and the clock. For a real world implementation of QCA architecture it is crucial to know accurately about the limits on the operational environment for any given QCA design. The operation of any given QCA architecture will depend on many real world variables such as operational temperature, layer separation etc. This paper is an inference drawn from the study of a QCA design of Half Adder and Full Adder and its simulated operation under variable temperature. The study has been made on average energy dissipation, temperature stability along with fault tolerance under dislocation and vacancy of cells. The analysis is been made using QCADesignerE 2.0.3 simulation tool.

关键词： adders cellular automata cmos logic circuits fault tolerance quantum dots VLSI Fault tolerance adders Cellular automata cmos logic circuits Quantum dots Very large scale integration temperature stability quanta full adder Operating Environment

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：