65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography

作     者：Asif, Shahzad Andersson, Oskar Rodrigues, Joachim Kong, Yinan 

作者机构：Macquarie Univ Dept Engn Sydney NSW Australia Lund Univ Dept Elect & Informat Technol Lund Sweden 

出 版 物：《IET COMPUTERS AND DIGITAL TECHNIQUES》 (IET计算机与数字技术)

年 卷 期：2018年第12卷第2期

页      面：62-67页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：public key cryptography residue number systems multiplying circuits CMOS logic circuits 65-nm CMOS low-energy RNS modular multiplier elliptic-curve cryptography algorithm modular multiplication Rivest-Shamir-Adleman cryptography algorithm elliptic curve point multiplication modular exponentiation Chinese remainder theorem residue number system 40-channel RNS moduli-set short-channel width ASIC energy dissipation low-voltage ECC energy-efficient ECC 

摘      要：Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest-Shamir-Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40-channel RNS moduli-set is proposed for this architecture to benefit from the short-channel width of the RNS moduli-set. The throughput of the architecture is enhanced by pipelining and pre-computations. The proposed architecture is fabricated as an ASIC using 65-nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25V. The maximum throughput of the proposed design is 1037Mbps while operating at a frequency of 162MHz with an energy dissipation of 48nJ. The proposed architecture enables the construction of low-voltage and energy-efficient ECCs.