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A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage (vol 15, pg 65, 2021)

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IET circuits DEVICES & SYSTEMS 2021年第7期15卷 695-695页

作者： Folla, J. K. Department of Physics Laboratory of Energy Electrical and Electronics Systems University of Yaoundé I Yaoundé Cameroon Multidisciplinary Laboratory (MLAB) International Centre for Theoretical Physics (ICTP) Trieste Italy Department of Physics Laboratory of Electronics and Automatics University of Douala Douala Cameroon Electrical and Electronics Engineering Xiamen University Malaysia Sepang Selangor Malaysia Electrical Electronic and Systems Engineering Universiti Kebangsaan Malaysia Bangi Selangor Malaysia

The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm cmos technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.

关键词： flip-flops energy 0.968 fJ low-power electronics enhanced differential pair amplifier custom latch structure voltage 1.0 V time 14.28 ps propagation delay short circuit current cmos technology process preamplifiers preamplifier module size 65 nm optimal time delay solution high-speed dynamic latch comparator frequency 20 GHz power dissipation corner analysis comparators (circuits) power consumption high-speed integrated circuits clocks low-offset low-power latch comparator clock frequency post-layout simulation cross-coupled transistors voltage 4.45 mV integrated circuit layout cmos logic circuits double tail comparator preamplifier-enhanced stage

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An effective nano design of demultiplexer architecture based on coplanar quantum-dot cellular automata

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IET circuits DEVICES & SYSTEMS 2021年第2期15卷 168-174页

作者： Afrooz, Sonia Navimipour, Nima Jafari Islamic Azad Univ Dept Comp Engn Tabriz Branch Tabriz Iran Natl Yunlin Univ Sci & Technol Future Technol Res Ctr 123 Univ Rd Sect 3 Touliu 64002 Yunlin Taiwan

Quantum-dot cellular automata (QCA) are prospective nanotechnology with striking performance to tackle the shortcomings of complementary metal-oxide-semiconductor (cmos) transistor-based technology such as fabrication dimensions and switching speed. The demultiplexer, as a crucial component for the design of many logic circuits, comprises a circuit for separating the multiplex data into the component data. The demultiplexer is highly utilised in the communication system for building serial data lines to parallel ones. So, its efficient schematisation has turned to an issue that has captured the concentration of the investigation group. Therefore, a novel structure of QCA-based one to two demultiplexers is proposed, and it is employed to design one to four demultiplexers. QCAdesigner software, as a powerful layout and tool for simulation, is utilised for evaluating the validity and practicality of the proposed structures. The detailed evaluation of proposed layouts shows excellent performance than prior operations, and notable developments regarding the occupied area, cell count, and latency.

关键词： multiplex data nanotechnology component data logic circuits cellular automata logic design switching speed demultiplexer architecture striking performance demultiplexing equipment quantum dots complementary metal-oxide-semiconductor transistor-based technology coplanar quantum-dot cellular automata QCA cmos logic circuits serial data lines

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Static power model for cmos and FPGA circuits

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IET COMPUTERS AND DIGITAL TECHNIQUES 2021年第4期15卷 263-278页

作者： Razzaq, Anas Ye, Andy Ryerson Univ Dept Elect & Comp Engn 350 Victoria St Toronto ON Canada

In Ultra-Low-Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time-consuming Spice simulations are used to measure the static power consumption. Herein, a technology-independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model, the effects of transistor sizing, transistor stacking, gate boosting and voltage change are considered. The procedure to apply this model to processors and FPGAs is demonstrated. Across different process technologies, compared to traditional spice simulation, this model can estimate the static power consumption of processor with an error of 1%-4%, while static power consumption of an FPGA system with an error of 1%-15%.

关键词： cmos logic circuits field programmable gate arrays integrated circuit modelling logic design low-power electronics power consumption SPICE

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Transmission Gate based Reordered Normal Basis Multiplier

Transmission Gate based Reordered Normal Basis Multiplier

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Devices for Integrated Circuit (DevIC)

作者： Bhavana Majji J. Pandu Department of Electronics and Communication Engineering Sreyas Institute of Engineering and Technology Hyderabad India

ISBN: (数字)9798350391107

ISBN: (纸本)9798350391114

This paper introduces the Transmission Gate-based Reordered Normal Basis (TGRNB) multiplier, which is a multiplication algorithm used in finite field arithmetic, It is crucial in many cryptographic applications, which aim to improve the performance and efficiency of Reordered Normal Basis (RNB) multiplications. This multiplier is implemented using transmission gates and compared with static cmos logic. The TGRNB multiplier utilizes transmission gates, which control the flow of signals in the circuit by allowing efficient implementation by reducing power consumption and increasing overall performance. The main advantage of TGRNB multiplier is its ability to perform operations in parallel, leading to significant speed improvements. Hence, this multiplier offers faster operation, higher power efficiency, and better adaptability compared to the static cmos implementation.

关键词： Power demand cmos logic circuits logic circuits logic gates Delays Cryptography Transistors logic Galois fields Arithmetic

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Modelling for triple gate spin-FET and design of triple gate spin-FET-based binary adder

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IET circuits DEVICES & SYSTEMS 2020年第4期14卷 464-470页

作者： Malik, Gul Faroz Ahmad Kharadi, Mubashir Ahmad Parveen, Nusrat Khanday, Farooq Ahmad Univ Kashmir Dept Elect & Instrumentat Technol Srinagar India Islamia Coll Sci & Commerce Dept Elect Srinagar India

In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of 3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained through XOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder, only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designed with cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reported work and conventional cmos design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional cmos designs.

关键词： logic gates field effect transistors optical logic adders indium compounds III-V semiconductors cmos logic circuits triple gate spin-FET-based binary adder triple-gate spin-FET spin diffusion length channel resistance junction polarisation 3-input XOR 3-input XNOR majority gate XOR gate 2-bit ripple adder cascading two 1-bit full-adders conventional cmos design indium arsenide channel-based triple gate spin-FET model InAs

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High-speed and area-efficient scalableN-bit digital comparator

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IET circuits DEVICES & SYSTEMS 2020年第4期14卷 450-458页

作者： Tyagi, Piyush Pandey, Rishikesh Thapar Inst Engn & Technol Dept Elect & Commun Engn Patiala Punjab India

An area-efficientN-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bitwidths, stages present in CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure. The FM validates the final comparison based on results obtained from the CEM. The presence of regular very large-scale integration topology in the proposed structure allows the analytical derivation of the area in terms of total number of transistors present in the design and total delay encountered in input-output flow as the function of input operand bitwidth. Spectre simulation results have been presented using 0.18 mu m complementary metal-oxide-semiconductor (cmos) technology at 1 GHz. The main advantages of the proposed comparator are minimum input-output delay of 0.57 ns, minimum fan-out-of-4 delay of 9.5 ns and low-power dissipation of 1.03 mw as compared with existing comparators designed using 180 nm cmos technology for 64 bit comparison.

关键词： cmos logic circuits comparators (circuits) integrated circuit design logic design low-power electronics VLSI digital comparator high operating speed low-power dissipation comparator structure comparison evaluation module CEM input operand bitwidth regular structure repeated logic cells parallel prefix tree structure very large-scale integration topology input-output flow Spectre simulation complementary metal-oxide-semiconductor technology minimum input-output delay area-efficient scalable N-bit digital comparator High-speed scalable N-bit digital comparator input operand bitwidths analytical derivation cmos technology size 0 18 mum frequency 1 0 GHz time 0 57 ns time 9 5 ns word length 64 0 bit power 1 03 mW

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Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g

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IET COMPUTERS AND DIGITAL TECHNIQUES 2020年第5期14卷 193-200页

作者： Kumar, Ganjikunta Ganesh Sahoo, Subhendu K. Sreenidhi Inst Sci & Technol Dept ECE Hyderabad India BITS Pilani Hyderabad Campus Dept EEE Hyderabad India

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W-32, W-64, and W-128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

关键词： OFDM modulation fast Fourier transforms field programmable gate arrays power consumption digital arithmetic cmos logic circuits Zigbee power-efficient variable-length fast Fourier transform MR-OFDM physical layer IEEE 802 15 4-g standard multirate orthogonal frequency division multiplexing physical layer multiregional orthogonal frequency division multiplexing physical layer mixed-radix algorithm configurable complex constant multiplier structure W-128 twiddle factor multiplication Altera field-programmable gate array devices mixed-radix FFT architecture variable-length FFT architecture gate count post-synthesis hardware cost reduction Xilinx Virtex-5 16-32-64-128-point single-path delay feedback pipeline fast Fourier transform architecture W-64 twiddle factor multiplication W-32 twiddle factor multiplication hardware-sharing mechanism memory space requirement reduction 128-point FFT complementary metal-oxide-semiconductor technology power consumption area-efficient variable-length fast Fourier transform size 90 0 nm voltage 1 0 V power 3 832 mW word length 12 bit

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Design and Analysis of Power-Efficient Quasi-Adiabatic Ternary Content Addressable Memory (QATCAM)

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IET circuits DEVICES & SYSTEMS 2020年第7期14卷 923-928页

作者： Durai, Jothi Rajagopal, Sivakumar Ganesan, Geetha RMK Engn Coll Dept Elect & Commun Engn Chennai 601206 Tamil Nadu India Vellore Inst Technol Sch Elect Engn Vellore 632014 Tamil Nadu India Anna Univ Dept Elect & Commun Engn CEG Chennai 600025 Tamil Nadu India

Ternary content addressable memory (TCAM) is a high-speed memory employed in network search engines which consume significant power. Many authors have provided efficient power solutions by proposing different match line schemes. This study proposes the use of energy recovering adiabatic logic scheme in the design of power-efficient TCAM. Two different innovative quasi-adiabatic TCAM (QATCAM) core cells are designed. The design is implemented in 180 nm complementary metal-oxide semiconductor technology with a power clock of 1.8 V on Cadence Virtuoso. It is found that the power dissipated by the proposed QATCAM cells is lower than its conventional counterparts. Adiabatic TCAM arrays are designed using adiabatic peripheral circuits. The proposed adiabatic TCAM core cells yield more considerable power savings even at higher frequencies up to 1 GHz.

关键词： content-addressable storage cmos logic circuits low-power electronics cmos integrated circuits clocks integrated circuit design search engines adiabatic logic scheme quasiadiabatic TCAM core cells complementary metal-oxide semiconductor technology power clock QATCAM cells adiabatic TCAM arrays adiabatic peripheral circuits adiabatic TCAM core cells network search engines power-efficiency quasiadiabatic ternary content addressable memory power-efficiency TCAM size 180 0 nm voltage 1 8 V frequency 1 0 GHz

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Gray-code adder with parity generator - a novel quantum-dot cellular automata implementation

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IET circuits DEVICES & SYSTEMS 2020年第2期14卷 243-250页

作者： Vieira, Luiz G. L. Vieira, Luiz F. M. Vieira, Marcos A. M. Vilela Neto, Omar P. Univ Fed Minas Gerais Comp Sci Dept Ave Antonio Carlos 6627 Belo Horizonte MG Brazil

This study describes the first Gray-code adder architecture, without the need to transform the Gray code into binary code, using the quantum-dot cellular automata (QCA). This device is a widely used resource for machine communications, counters, and encoders. QCA is a possible alternative to the current integrated circuit [complementary metal oxide semiconductor (cmos)] due to its nanometric scale and very low-power consumption. In a bottom-up approach, the authors first describe and present the architecture of an important building block that composes the Gray-code adder, the parity generator, and then describe the full architecture. Besides being essential in the proposed adder, the parity generator is also important for error-checking and construction of other devices and widely used in communications. They demonstrate the functionality, test, and validate the proposed architectures using the QCADesigner simulator. If QCA consolidates as a possible cmos substitute, this study can impact the design of future components that uses Gray-code and parity generator, such as embedded digital communications systems that will benefit from the low-power consumption of the QCA technology.

关键词： adders Gray codes binary codes cellular automata quantum dots parity check codes low-power electronics cmos logic circuits parity generator quantum-dot cellular automata binary code QCADesigner simulator low-power consumption current integrated circuit Gray-code adder machine communications complementary metal oxide semiconductor cmos embedded digital communication

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High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4:2 compressor design in CNFET technology

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IET circuits DEVICES & SYSTEMS 2020年第3期14卷 357-368页

作者： Avan, Amin Maleknejad, Mojtaba Navi, Keivan Shahid Beheshti Univ Fac Comp Sci & Engn GC Tehran Iran Islamic Azad Univ Dept Comp Engn Sci & Res Branch Tehran Iran

Compressors are fundamental components in multi-operand addition and multiplication hardware. The present study aims to propose several high-speed hybrid designs of 4:2 compressors which are implemented based on multi-threshold logic and transmission gate multiplexers, at low supply voltages. In order to implement these circuits, carbon nanotube field-effect transistors (CNFETs) are utilised. The division of the entire input capacitor network in the third proposed design causes the entire structure operates faster and consumes less power. All designs were simulated with Synopsys HSPICE and $32\, {\rm nm}$32nm CNFET technology in different conditions. Simulation results demonstrate the superiority of the third proposed design with regard to different load and frequency conditions. In addition, it becomes less sensitive to process, voltage and temperature variations compared to other similar capacitive threshold logic circuits. The results indicate the third proposed design outperforms the best reference design in terms of delay and power-delay product by 34 and 25%, respectively. Furthermore, the performance of each design was evaluated in a 8 x 8-bit binary multiplier as a uniform test bench, which confirmed the above results on isolated single 4:2 compressors.

关键词： cmos logic circuits carbon nanotube field effect transistors multiplying circuits logic design logic gates threshold logic low-power electronics field effect transistor circuits capacitors CNFET technology multioperand addition multiplication hardware high-speed hybrid designs transmission gate multiplexers low supply voltages carbon nanotube field-effect transistors entire input capacitor network frequency conditions temperature variations similar capacitive threshold logic circuits reference design high-speed energy efficient process temperature tolerant hybrid multithreshold 4:2 compressor design multithreshold logic input capacitor network Synopsys HSPICE process-voltage-temperature variations capacitive threshold logic circuits power-delay product binary multiplier uniform test bench isolated single 4:2 compressors size 32 0 nm

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