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International Workshop on Information and Electronics Engineering (IWIEE) / International Conference on Information, Computing and Telecommunications (ICICT)

作者： Ye, Junming Zhou, Guangxiang Liu, Haiyan Guilin Univ Elect Technol Guilin 54100 Guangxi Peoples R China

In order to improve anti-jamming performance of the sensor, fast lock digital PLL is proposed and the PLL is used in the sensor. Digital PLL with a simple structure, flexible control, high tracking accuracy, loop performance and easy integration of features;while PLL loop automatic variable in the model control technology to speed up the rate locked loop to reduce Phase jitter. In this paper, the arithmetic average and moving average value of the software filter scheme to solve the sensor can filter out high frequency interference filter design problems and improve robustness. (C) 2011 Published by Elsevier Ltd.

关键词： Digital Phase - Locked Loop complex programmable logic device verilog

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Design and Research of Improved Digital Phase-Locked Loop Based on FPGA

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Procedia Engineering 2012年 29卷 547-552页

作者： Junming Ye Guangxiang Zhou Haiyan Liu Guilin University of Electronic Technology Guilin 54100GuangxiChina

In order to improve anti-jamming performance of the sensor, fast lock digital PLL is proposed and the PLL is used in the sensor. Digital PLL with a simple structure, flexible control, high tracking accuracy, loop performance and easy integration of features; while PLL loop automatic variable in the model control technology to speed up the rate locked loop to reduce Phase jitter. In this paper, the arithmetic average and moving average value of the software filter scheme to solve the sensor can filter out high frequency interference filter design problems and improve robustness.

关键词： Digital Phase - Locked Loop complex programmable logic device Verilog

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THE DESIGN AND IMPLEMENTATION OF A SPREAD SPECTRUM COMMUNICATION SYNCHRONOUS SYSTEM BASED ON CPLD

THE DESIGN AND IMPLEMENTATION OF A SPREAD SPECTRUM COMMUNICA...

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2009中国宁波国际计算机科学与技术学术大会

作者： Hengjun Zhu Yuedou Qi Hui Li Hongbo Yu Qiqihar University Communication and Electronic Engineering College Software College Ningbo Dahongying University

This paper proposed a design and implementation for CDMA spread spectrum communication synchronous system based on the MAX7000 *** system is developed in the development environment of Quartus II with the complex programmable logic devices and hardware description *** simulation results showed that the verification of synchronous sequential logic is correct and the information transmission is *** scheme with low cost and easy development has certain significance for teaching and scientific research.

关键词： Spread Spectrum Communication Synchronization System complex programmable logic device Hardware Description Language

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Efficient sequential switching hybrid modulation techniques for multiphase multilevel inverters

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IET POWER ELECTRONICS 2011年第5期4卷 557-569页

作者： Govindaraju, C. Govt Coll Engn Dept Elect & Elect Engn Salem India

This study presents certain sequential switching hybrid modulation strategies, and compared for multiphase multilevel inverters. Hybrid modulation represents the combination of fundamental frequency, and multilevel sinusoidal modulations and designed for performance of the well-known alternative phase opposition disposition, phase shifted carrier, carrier-based space vector modulation and single-carrier sinusoidal modulations. The main characteristic of these modulations are the reduction of switching losses with good harmonic performance. A simple sequential switching and base pulse-width modulation (PWM) circulation techniques are embedded with these modulations, to achieve balanced power dissipation among the devices within a cell and for series connected cells, equal load sharing and balanced DC-link capacitor voltages. Multilevel sinusoidal PWM and its base modulation design are implemented on a TMS320F2407 digital signal processor (DSP). complex programmable logic device realises hybrid control algorithm with base PWM circulation and integrated with DSP for sequential switching hybrid PWM generation. The feasibility of these modulations are theoretically analysed for five-level and then generalised for N-level, validated by simulation and confirmed practically for a five-level inverter.

关键词： switching loss logic and switching circuits alternative phase opposition disposition single-carrier sinusoidal modulation logic circuits phase shifted carrier multilevel sinusoidal modulation load sharing DSP sequential switching hybrid modulation technique PWM invertors Digital signal processing chips balanced DC-link capacitor voltage carrier-based space vector modulation Power convertors and power supplies to apparatus digital signal processor hybrid control algorithm PWM circulation technique multiphase multilevel inverter programmable logic devices digital signal processing chips complex programmable logic device pulse width modulation circulation technique balanced power dissipation

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A Low-Power Digital Frequency Divider for System-on-a-Chip Applications

A Low-Power Digital Frequency Divider for System-on-a-Chip A...

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54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Omran, Hesham Sharaf, Khaled Ibrahim, Magdi King Abdullah Univ Sci & Technol Elect Engn Program Thuwal 239556900 Saudi Arabia Ain Shams Univ Elect & Commun Engn Dept Fac Engn Cairo Egypt

ISBN: (纸本)9781612848570

In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%.

关键词： CPLD Engines Universal Serial Bus coarse-fine architecture complex programmable logic device frequency dividers input frequency low-power digital frequency divider low-power electronics lower power consumption programmable logic devices synchronous divider system-on-a-chip applications system-on-chip

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MODEL AND ITS REALIZATION FOR A SPREAD SPECTRUM COMMUNICATION SYNCHRONOUS SYSTEM

MODEL AND ITS REALIZATION FOR A SPREAD SPECTRUM COMMUNICATIO...

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The 2010 International Conference on Computer Application and System Modeling(2010计算机应用与系统建模国际会议 ICCASM 2010)

作者： Yuedou Qi Hengjun Zhu Ningbo Dahongying University College of Software Ningbo P.R.China 315175 Qiqihar University Communication and Electronic Engineering College Qiqihar P.R.China 161005

ISBN: (纸本)9781424472352

This paper proposed a design and implementation for CDMA spread spectrum communication synchronous system based on the MAX7000 device. The system is developed in the development environment of Quartus II with the complex programmable logic devices and hardware description languages. The simulation results showed that the verification of synchronous sequential logic is correct and the information transmission is distortion-less. The scheme with low cost and easy development has certain significance for teaching and scientific research.

关键词： synchronization system hopping complex programmable logic device hardware description language

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Research on synchronous generator automatic quasi-synchronising device

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INTERNATIONAL JOURNAL OF MODELLING IDENTIFICATION AND CONTROL 2009年第4期7卷 388-391页

作者： Zhang, Xiaoying Dang, Cunlu Chai, Li Lanzhou Univ Technol Sch Elect & Informat Engn Lanzhou 730050 Gansu Peoples R China

Generator synchronising is an important and frequent operation in the power system. A new-style generator quasi-synchronising device based on AT89S52 SCM and CPLD is studied in this paper. In order to avoid great impact current, the voltage magnitude, frequency and phase difference between two sides of the breaker must be permitted, otherwise the frequency and the voltage of the generator will be adjusted. The AT89S52 and CPLD act as the core in the hardware design and the hardware includes eight modules. The configuration program idea is adopted in the software design which includes main program and many subprograms. The structure of the device is simple, the reliability is high and the maintenance is easy. The measures of the frequency, voltage and phase are automatically finished and the intelligent frequency and voltage adjustments are realised in the new synchronising device. The simple interface makes parameters setup simple. The functions of the sample are steady and dependable after running for several months.

关键词： automatic quasi-synchronising single chip multiprocessor SCM complex programmable logic device CPLD synchronous generator automatic measure intelligent adjustment simulation

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A Reconfigurable Quadrature Decoder of Motor

A Reconfigurable Quadrature Decoder of Motor

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27th Chinese Control Conference

作者： Lv Changzhi Fan Di Shandong Univ Sci & Technol Coll Informat & Elect Engn Qingdao 266510 Peoples R China

ISBN: (纸本)9787900719706

Quadrature decode technology is widely used in high accurate motor monitoring. But by now, the commercial quadrature decoder is not ideal because of its complex structure, high price, unchangeable counter and output interface, In this paper, a method is presented to optimize the quadrature encode signal according to its property, the modules to filter, quadruplicate and distinguish direction and the controller to reconfigurate the counter and output-bus are designed and integrated in one CPLD in virtue of ISP technology. The modules and controller are programmed with VHDL on Quartus II and simulated. The results of testing show that this decoder is robust and. easy to be maintained and upgraded besides of its high resolution and flexible interface.

关键词： Motor Quadrature decoder Reconfigurable complex programmable logic device Very High Speed Integrated Circuit Hardware Description Language

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A Versatile High-speed Image Processing System Based on DSP and CPLD

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Journal of Electronic Science and Technology of China 2006年第2期4卷 110-113页

作者：骆彦行解梅 School of Electronics Engineering University of Electronic Science and Technology of China Chengdu 610054 China

In this paper, we present an optimized design method for high-speed embedded image processing system using 32 bit floating-point Digital Signal Processor （DSP） and complex programmable logic device （CPLD）. The DSP acts as the main processor of the system： executes digital image processing algorithms and operates other devices such as image sensor and CPLD. The CPLD is used to acquire images and achieve complex logic control of the whole system. Some key technologies are introduced to enhance the performance of our system. In particular, the use of DSP/BIOS tool to develop DSP applications makes our program run much more efficiently. As a result, this system can provide an excellent computing platform not only for executing complex image processing algorithms, but also for other digital signal processing or multi-channel data collection by choosing different sensors or Analog-to-Digital （A/D） converters.

关键词： image processing digital signal processor complex programmable logic device DSP/BIOS

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Long-duration pulse generator

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He Jishu/Nuclear Techniques 2006年第5期29卷 396-400页

作者： Li, Suqin Su, Hong Li, Yong Qian, Yi Peng, Yu Dong, Chengfu Li, Xiaogang Ma, Xiaoli Institute of Modern Physics Chinese Academy of Sciences Lanzhou 730000 China Graduate School Chinese Academy of Sciences Beijing 100049 China

A CPLD-based long-duration pulse generator, which can generate singular or continuous pulse with ultra-low repetition rate/long cycle, is introduced in this paper. The cycle (T) of output pulses generated by this generator can be selected in a range from Tmin=1 ms to Tmin>1000 s. Also, the width of the output pulse can be adjusted from 1/1000 cycle to 999/1000 cycle stepped by 1/1000 cycle. Accuracy of the repetition rate (f) of output pulses is less than or equal 0.02 [per mille] , and the long-term instability is within ±0.01 [per mille] . There are two modes selectable for output pulses, singular pulse output and repetitive pulse output, which can be set by a two-position switch. When the singular pulse output mode is selected, only one pulse can be generated each time by pressing an external control push-button. This pulser can provide both TTL/T over-bar T over-bar L over-bar output signals and NIM/N over-bar I over-bar M over-bar output signals. The rise time of the NIM output signal is tr less than or equal 4 ns and the fall time is tf less than or equal 4 ns. We use CPLD to construct the main circuits. Compared with the circuits constructed by TTL devices, the new pulse generator has features such as less components, lower cost and lower dissipation.

关键词： complex programmable logic device Generator Long-duration pulse width Signals Ultra-low repetition rate

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