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41st Annual Nuclear and Space Radiation Effects Conference

作者： Nicolescu, B Savaria, Y Velazco, R Ecole Polytech Montreal PQ H3T 1J4 Canada TIMA Lab Circuits Qualificat Grp F-38031 Grenoble France

Increasing design complexity for current and future generations of microelectronic technologies leads to an increased sensitivity to transient bit-flip errors. These errors can cause unpredictable behaviors and corrupt data integrity and system availability. This paper proposes new solutions to detect all classes of faults, including those that escape conventional software detection mechanisms, allowing full protection against transient bit-flip errors. The proposed solutions, particularly well suited for low-cost safety-critical microprocessor-based applications, have been validated through exhaustive fault injection experiments performed on a set of real and synthetic benchmark programs. The fault model taken into consideration was single bit-flip errors corrupting memory cells accessible to the user by means of the processor instruction set. The obtained results demonstrate the effectiveness of the proposed solutions.

关键词： control flow checking data computing block (DCB) exhaustive fault injection experiments signature monitoring technique software error detection

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Design and evaluation of system-level checks for on-line control flow error detection

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1999年第6期10卷 627-641页

作者： Alkhalifa, Z Nair, VSS Krishnamurthy, N Abraham, JA So Methodist Univ Dept Comp Sci & Engn Dallas TX 75275 USA Motorola PowerPC Design Ctr Austin TX USA Univ Texas Comp Engn Res Ctr Austin TX 78712 USA

This paper evaluates the concurrent error detection capabilities of system-level checks, using fault and error injection. The checks comprise application and system level mechanisms to detect control flow errors. We propose Enhanced control-flow checking Using Assertions (ECCA). In ECCA, branch-free intervals (BFI) in a given high or intermediate level program are identified and the entry and exit points of the intervals are determined. BFIs are then grouped into blocks, the size of which is determined through a performance/overhead analysis. The blocks are then fortified with preinserted assertions. For the high level ECCA, we describe an implementation of ECCA through a preprocessor that will automatically insert the necessary assertions into the program. Then, we describe the intermediate implementation possible through modifications made on gee to make it ECCA capable. The fault detection capabilities of the checks are evaluated both analytically and experimentally. Fault injection experiments are conducted using FERRARI [1] to determine the fault coverage of the proposed techniques.

关键词： control flow checking assertions fault injection coverage latency

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Multiprocessor checking using watchdog processors

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COMPUTER SYSTEMS SCIENCE AND ENGINEERING 1996年第5期11卷 301-310页

作者： Majzik, I Hohl, W Pataricza, A Sieh, V UNIV ERLANGEN NURNBERG IMMD 3D-8520 ERLANGENGERMANY

A new control flow checking scheme is presented, based on assigned-signature checking using a watchdog processor. This scheme is suitable for a multitasking, multiprocessor environment. The hardware overhead is comparatively low because of three reasons: first, hierarchically structured, the scheme uses only a single watchdog processor to monitor processes on multiple processors. Second, as an assigned-signature scheme, it does not require monitoring the instruction bus of the processors. Third, the run-time and reference signatures are embedded into the checked program;thus, in the watchdog processor neither a reference database nor a time-consuming search and compare engine is required.

关键词： multiprocessor checking watchdog processors control flow checking

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A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS AND ITS ERROR-DETECTION CAPABILITY

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1994年第11期5卷 1169-1184页

作者： HANCU, MVA IWASAKI, K SATO, Y SUGIE, M CHIBA UNIV FAC ENGNDEPT INFORMAT & COMP SCICHIBA 260JAPAN HITACHI LTD CENT RES LABKOKUBUNJITOKYO 185JAPAN

This paper presents new principles for the on-line monitoring in the context of multiprocessors (especially massively parallel processors) and then focuses on the effect of the aliasing probability on the error detection process. In the proposed test architecture, the concurrent testing (or on-line monitoring) at system level is accomplished by enforcing the runtime test of the data and control dependences of the algorithm currently executed in the parallel computer. In order to help in this process, each message contains both source and destination addresses. At each message source, the sequence of destination addresses of the outgoing messages is compressed on a block basis. At the same time, at each destination;the sequence of source addresses of all incoming messages is compressed, also on a block basis. Concurrent compression of the instructions executed by the PE's is also possible. As a result of this procedure, an image of the data dependences and bf the control flow of the currently run algorithm is created. This image is compared at the end of each computational block with a reference image created at compilation time. The main results of this work are in proposing new principles for the on-line system-level test of multiprocessors systems,based on signaturing and monitoring the data dependences together with the control dependences, and in providing an analytical model and analysis for the address compression process used for the monitoring the data routing process.

关键词： ALIASING PROBABILITY CONCURRENT TESTING control flow checking DATA DEPENDENCE checking MASSIVELY PARALLEL COMPUTERS ONLINE ERROR-DETECTION PACKET-SWITCHED ROUTING PARALLEL COMPUTING SIGNATURE ANALYSIS SYSTEM-LEVEL ERROR DETECTION

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Enhancing on-line testability during synthesis

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Journal of Electronic Testing 1993年第1期4卷 105-116页

作者： Eschermann, Bernhard FB 12-Rechnerstrukturen Universität-GH-Siegen Siegen 5900 Hölderlinstr 3 Germany

If off-line testing is complemented by on-line checks, in general some of the test hardware is only used either for on-line checking (e.g., control flow monitors) or for production testing (e.g., pattern generators). In this article a hardware structure for controllers is presented, in which the complete test circuitry can be used for both facilitating a self-test and for checking the control flow during normal operation. The corresponding design procedure considers this target structure while synthesizing the controller from a behavioral description and thus minimizes the hardware overhead. Existing approaches for designing concurrently checked controllers can be represented as special cases in the formal framework established in this article. © 1993 Kluwer Academic Publishers.

关键词： BIST control flow checking controller synthesis synthesis for testability

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EXPERIMENTAL RESULTS ON THE ERROR-DETECTION CAPABILITY OF A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS

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PARALLEL COMPUTING 1992年第10期18卷 1079-1103页

作者： HANCU, MVA IWASAKI, K SATO, Y SUGIE, M CHIBA UNIV FAC ENGNDEPT INFORMAT & COMP SCICHIBA 260JAPAN HITACHI LTD CENT RES LABKOKUBUNJITOKYO 185JAPAN

In a previous paper, we introduced a new concurrent testing (or on-line monitoring) architecture for Massively-Parallel Computers. In the proposed test architecture, on-line checks for both control flow and data Touting are accomplished by enforcing the run-time test of compressed (signatured) versions of the control and data dependences of the algorithm executed in the parallel computer. This paper focuses on the results of simulation experiments on the error detection of the proposed test architecture as applied to the routing process. Four sets of experiments were executed, with two compressors or signature analyzers (an MISR and an LFSR) and two error models (the 2m-ary and the Binary Symmetric Channel). Using a randomized routing process and a randomized fault insertion, we have obtained detailed figures for the undetected errors at all crucial detecting points of our proposed detection method: the source, the expected destination and the false destination of the messages. High detection ratios for multiple errors were obtained for compressors of only moderate size, supporting the use of this method in practical applications. The results are independent of the topology of the interconnection network and the detailed routing algorithm.

关键词： ALIASING PROBABILITY CONCURRENT TESTING control flow checking DATA DEPENDENCE checking MASSIVELY-PARALLEL COMPUTERS ONLINE ERROR-DETECTION, PACKET-SWITCHED ROUTING PARALLEL COMPUTING SIGNATURE ANALYSIS SYSTEM-LEVEL ERROR DETECTION

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VERIFICATION OF CONCURRENT control flow IN DISTRIBUTED COMPUTER-SYSTEMS

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1988年第4期14卷 405-417页

作者： YAU, SS HONG, WM Department of Electrical Engineering and Computer Science Northwestern University Evanston IL 60201

An approach to verifying control flow in distributed computer systems (DCS) is presented. The approach is based on control flow checking among software components distributed over processors and cooperating among them. In this approach, control flow behavior of DCS software is modeled and contained in special software components called verifiers. The verifiers are distributed over the processors and consulted to check the correctness of the control flow in DCS soft- ware during its execution. Algorithms for deriving the verifiers are presented. This technique can detect global errors including synchronization errors as well as local errors. It can be used for sequential or concurrent software at various levels of details. Experiments show that using this technique requires no significant overhead. [ABSTRACT FROM AUTHOR]

关键词： control flow checking distributed software fault-tolerance Index Terms-Context-free grammar software design representation

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A ROVING MONITORING PROCESSOR FOR DETECTION OF control flow ERRORS IN MULTIPLE PROCESSOR SYSTEMS

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1987年第4-5期20卷 249-269页

作者： SHEN, JP TOMAS, SP CARNEGIE MELLON UNIV DEPT ELECT & COMP ENGNPITTSBURGHPA 15213

This paper presents a new concept of on-line control flow monitoring called Roving Monitoring. This technique utilizes a special purpose roving monitoring processor in order to provide continuous and concurrent checking of instruction level control flow in multiple processor systems. The roving monitoring processor is time shared among several application processors to reduce overall monitoring overhead. The design and implementation of a roving monitoring processor with a novel architecture is presented. The roving monitoring concept is shown to be quite feasible.

关键词： Fault Detection On-Line Monitoring Multiple Processor Systems Roving Monitoring control flow checking

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AN APPROACH TO CONCURRENT control flow checking

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1980年第2期6卷 126-137页

作者： YAU, SS CHEN, FC Department of Electrical Engineering and Computer Science Northwestern University

A control flow checking scheme capable of detecting control flow errors of programs resulting from software coding errors, hardware malfunctions, or memory mutilation during the execution of the program is presented. In this approach, the program is partitioned into loop-free intervals and a database containing the path information in each of the loop-free intervals is derived from the detailed design. The path in each loop-free interval actually traversed at run time is recorded and then checked against the information provided in the database, and any discrepancy indicates an error. This approach is general, and can detect all uncompensated illegal branches. Any uncompensated error that occurs during the execution of a loop-free interval and manifests itself as a wrong branch within the loop-free interval or right after the completion of execution of the loop-free interval is also detectable. The approach can also be used to check the control flow in the testing phase of program development. The capabilities, limitations, implementation, and the overhead of using this approach are discussed.

关键词： Wrong Branches Algorithms Capabilities Concurrency control Errors control flow checking Illegal Branches Implementation Limitations Loop Free Intervals Overhead Path Representation Program Design

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