A parametric analysis was performed on the parameters affecting ground fault current division in order to determine the critical parameters. Then, a method of graphically determining the maximum grid current for use i...
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A parametric analysis was performed on the parameters affecting ground fault current division in order to determine the critical parameters. Then, a method of graphically determining the maximum grid current for use in designing substation grounding systems was developed. The curves were based on results using the substation maximum earth current computation (SMECC) program developed for EPRI. The graphical analysis is not intended as an accurate replacement for computer program analysis (such as SMECC), but rather it is intended as a means for quickly determining a reasonable approximation of the maximum grid current for the preliminary grounding system design. In some cases, the graphical analysis result in sufficient accuracy to make more exact analysis unnecessary.
dataflow languages enable describing signal processing applications in a platform independent fashion, which makes them attractive in today's multiprocessing era. RVC-CAL is a dynamic dataflow language that enable...
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dataflow languages enable describing signal processing applications in a platform independent fashion, which makes them attractive in today's multiprocessing era. RVC-CAL is a dynamic dataflow language that enables describing complex data-dependent programs such as video decoders. To this date, design automation toolchains for RVC-CAL have enabled creating workstation software, dedicated hardware and embedded application specific multiprocessor implementations out of RVC-CAL programs. However, no solution has been presented for executing RVC-CAL applications on generic embedded multiprocessing platforms. This paper presents a dataflow-based multiprocessor communication model, an architecture prototype that uses it and an automated toolchain for instantiating such a platform and the software for it. The complexity of the platform increases linearly as the number of processors is increased. The experiments in this paper use several instances of the proposed platform, with different numbers of processors. An MPEG-4 video decoder is mapped to the platform and executed on it. Benchmarks are performed on an FPGA board.
A methodology for automatically deriving image processing ASIC's from their real-time emulation on the data-flow functional computer is presented, The aim of the method is to reduce the time and effort required to...
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A methodology for automatically deriving image processing ASIC's from their real-time emulation on the data-flow functional computer is presented, The aim of the method is to reduce the time and effort required to synthesize and validate ASIC's after emulation, This is achieved by optimizing the architecture validated on the emulator and integrating the optimized resources, The paper presents the derivation of a 1100 MIPS defect detector.
The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisi...
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The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.
An implementation of the ray-tracing algorithm that is based on the Voxar parallel processing model, which simulates 3D physical phenomena, is discussed. The implementation of a general parallel ray-tracing program, a...
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An implementation of the ray-tracing algorithm that is based on the Voxar parallel processing model, which simulates 3D physical phenomena, is discussed. The implementation of a general parallel ray-tracing program, and the implementation of Voxar are reviewed. Results of a performance evaluation of Voxar show that the machine's best points are its efficiency on complex ray-tree images and its parallel animation functionality. Its weak points are the insufficiency of the deadlock prevention strategy, the high cost of the communication system, the sequential generation of the primary rays, and the rigidity of the regular subdivision.
This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessor array. Based on the notion of computational wavefront, the hardware of the processo...
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This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessor array. Based on the notion of computational wavefront, the hardware of the processor array is designed to provide a computing medium that preserves the key properties of the wavefront. In conjunction, a wavefront language (MDFL) is introduced that drastically reduces the complexity of the description of parallel algorithms and simulates the wavefront propagation across the computing network. Together, the hardware and the language lead to a programmable wavefront array processor (WAP). The WAP blends the advantages of the dedicated systolic array and the general-purpose data-flow machine, and provides a powerful tool for the high-speed execution of a large class of matrix operations and related algorithms which have widespread applications.
Improvements in data acquisition and processing techniques have led to an almost continuous flow of information for financial data. High-resolution tick data are available and can be quite conveniently described by a ...
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Improvements in data acquisition and processing techniques have led to an almost continuous flow of information for financial data. High-resolution tick data are available and can be quite conveniently described by a continuous-time process. It is therefore natural to ask for possible extensions of financial time series models to a functional setup. In this paper we propose a functional version of the popular autoregressive conditional heteroskedasticity model. We will establish conditions for the existence of a strictly stationary solution, derive weak dependence and moment conditions, show consistency of the estimators, and perform a small empirical study demonstrating how our model matches with real data.
For Integrated Vehicle Health Management (IVHM) technology to fully achieve its promise, there is a need for integration architecture to support interoperability between multiple vendors' IVHM components and inser...
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For Integrated Vehicle Health Management (IVHM) technology to fully achieve its promise, there is a need for integration architecture to support interoperability between multiple vendors' IVHM components and insertion of new IVHM capabilities. To date there have been very limited studies on different approaches in integrating IVHM components. This paper presents design candidates for plug-and-play (PnP) IVHM architecture. The open standard based designs are derived from desired IVHM dataflow characteristics and system configuration requirements. The designs and enabling middleware technologies are qualitatively and empirically evaluated for their adequacy and effectiveness. The qualitative assessment focuses on the implementation and system configuration based on different test scenarios. The empirical performance is measured in terms of latency (in both normal and intermittent network connections) and throughput. The results identify the advantages and disadvantages in the different designs of PnP IVHM architecture in which ease of configuration, performance and applicable data buses are the main conflicting objectives.
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