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High Performance Stereo Vision Designed for Massively data parallel Platforms

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2010年第11期20卷 1509-1519页

作者： Yu, Wei Chen, Tsuhan Franchetti, Franz Hoe, James C. Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA

Real-time stereo vision is attractive in many applications like robot navigation and 3-D scene reconstruction. data parallel platforms, e. g., graphics processing unit (GPU), are often used for real-time stereo, because most stereo algorithms involve a large portion of data parallel computations. In this paper, we propose a stereo system on GPU which pushes the Pareto-efficiency frontline in the accuracy and speed tradeoff space. Our system is based on a hardware-aware algorithm design approach. The system consists of new algorithms and code optimization techniques. We emphasize on keeping the highly data parallel structure in the algorithm design process such that the algorithms can be effectively mapped to massively data parallel platforms. We propose two stereo algorithms: namely, exponential step size adaptive weight (ESAW), and exponential step size message propagation (ESMP). ESAW reduces computational complexity without sacrificing disparity accuracy. ESMP is an extension of ESAW, which incorporates the smoothness term to better model non-frontal planes. ESMP offers additional choice in the accuracy and speed tradeoff space. We adopt code optimization methodologies from the performance tuning community, and apply them to this specific application. Such an approach gives higher performance than optimizing the code in an "ad hoc" manner, and helps understanding the code efficiency. Experiment results demonstrate a speedup factor of 2.7-8.5 over state-of-the-art stereo systems at comparable disparity accuracy.

关键词： Code optimization data parallel graphics processing unit (GPU) multicore real-time stereo

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SEMANTICS FOR data parallel COMPUTATION

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INTERNATIONAL JOURNAL OF parallel PROGRAMMING 1990年第6期19卷 477-509页

作者： RICE, MD WESLEYAN UNIV DEPT MATHMIDDLETOWNCT 06459

The paper describes the semantics of an elementary language for data parallel computation that is based on an abstract parallel machine. The semantics of the language is described in both a mathematical and an operational manner. The mathematical semantics can be used to prove the correctness of algorithms specified in the language. The operational semantics provides a CSP description of an abstract machine that can be used to execute programs written in the language. The latter portion of the paper establishes that the two semantic descriptions are equivalent.

关键词： ALGORITHM CSP data parallel SEMANTICS SIMD

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A study of 3D Network-on-Chip design for data parallel H.264 coding

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MICROPROCESSORS AND MICROSYSTEMS 2011年第7期35卷 603-612页

作者： Xu, Thomas Canhao Yin, Alexander Wei Liljeberg, Pasi Tenhunen, Hannu Univ Turku Dept Informat Technol FIN-20520 Turku Finland Turku Ctr Comp Sci Turku 20520 Finland

In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 20 design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications. Crown Copyright (C) 2011 Published by Elsevier B.V. All rights reserved.

关键词： Network-on-Chip 3D IC design H.264 Coding data parallel

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parallel image processing with the block data parallel architecture

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PROCEEDINGS OF THE IEEE 1996年第7期84卷 947-968页

作者： Alexander, WE Reeves, DS Gloster, CS N CAROLINA STATE UNIV DEPT COMP SCIRALEIGHNC 27695

Many digital signal and image processing algorithms can be speeded up by executing them in parallel on multiple processors. The speed of parallel execution is limited by the need for communication and synchronization between processors. In this paper, we present a paradigm for parallel processing that we call the block data flow paradigm (BDFP). The goal of this paradigm-is to reduce interprocessor communication, and relax the synchronization requirements for such applications. We present the block data parallel architecture which implements this paradigm, and we present methods for mapping algorithms onto this architecture. We illustrate this methodology for several applications including two-dimensional (2-D) digital filters, the 2-D discrete cosine transform, QR decomposition of a matrix, and Cholesky factorization of a matrix. We analyze the resulting system performance for these applications with regard to speedup and efficiency as the number of processors increases. Our results demonstrate that the block data parallel architecture is a flexible, high-performance solution for numerous digital signal and image processing algorithms.

关键词： ARCHITECTURE System performance PROCESSOR Image processing interprocessor communication Cholesky factorisation Building construction data parallel image processing algorithm parallel Lines parallel execution digital signals

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SCALABLE data-parallel ALGORITHMS FOR TEXTURE SYNTHESIS USING GIBBS RANDOM-FIELDS

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IEEE TRANSACTIONS ON IMAGE PROCESSING 1995年第10期4卷 1456-1460页

作者： BADER, DA JALA, J CHELLAPPA, R UNIV MARYLAND INST ADV COMP STUDIESCOLLEGE PKMD 20742

This correspondence introduces scalable data parallel algorithms for image processing. Focusing on Gibbs and Markov random field model representation for textures, we present parallel algorithms for texture synthesis, compression, and maximum likelihood parameter estimation, currently implemented on Thinking Machines CM-2 and CM-5. Use of fine-grained, data parcel processing techniques yields real-time algorithms for texture synthesis and compression that are substantially faster than the previously known sequential implementations. Although current implementations are on Connection Machines, the methodology presented here enables machine-independent scalable algorithms for a number of problems in image processing and analysis.

关键词： parallel algorithms Image processing data parallel algorithms Scalability maximum likelihood estimation Markov random fields texture synthesis

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Ultra-high performance, low-power, data parallel radar implementations

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IEEE AEROSPACE AND ELECTRONIC SYSTEMS MAGAZINE 2006年第4期21卷 3-7页

作者： Reddaway, SF Bruno, P Rogina, P Pancoast, R WorldScape Baldock SG7 5QE Herts England

Radar involves similar operations applied to large amounts of data. It is thus well suited to data parallel (SIMD) hardware. In the past, large data-parallel machines have been applied to radar with limited success. This has been due to such reasons as programming issues, cost, and the hardware being too big for most embedded applications. Most SIMD machines went away a decade ago. There is now a new generation of SIMD COTS technology with powerful Processing Elements (PEs) and floating-point hardware. WorldScape is applying these chips to radar processing, and has demonstrated significantly more performance with much lower power dissipation (GFLOPS/Watt). These implementations provide attractive alternatives to traditional FPGA and DSP solutions. Lockheed-Martin has provided benchmark validation testing and support for these implementations. The current implementation is based on a 64 PE, 25 GFLOP CS-301 chip supplied by ClearSpeed Technology PLC. WorldScape has demonstrated FFT, Pulse Compression, a form of QR factorization, and other applications on this generation of hardware using a mix of C-level programming and optimized assembly. The next generation chip is compatible, but also has several improvements that will significantly enhance I/O performance as well as raw GFLOP throughput. An updated demonstration and discussion of a Scalable Processing Platform for embedded radar processing which significantly improves I/O performance and provides a roadmap to government-qualified hardware for technology insertion. Architectures, data parallel coding approaches, additional functionality of the Scalable Processing Platform, and relevance to embedded defense radar applications will be discussed.

关键词： digital signal processing chips low-power electronics military radar radar equipment radar signal processing C-level programming ClearSpeed Technology PLC DSP solutions FFT GFLOP Lockheed-Martin QR factorization SBVED machines SIMD COTS technology WorldS data parallel Military radar low-power electronics radar Radar signal processing Fast Fourier transform Radar equipment Computer hardware digital signal processing chips

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data-parallel computing

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Queue 2008年第2期6卷 30-39页

作者： Boyd, Chas. Microsoft

No abstract available

关键词： PROCESSOR Processor Core Metals performance boost data parallel Leverage coding get

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Parallaxis-III:: Architecture-independent data parallel processing

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 2000年第3期26卷 227-243页

作者： Bräunl, T Univ Western Australia Mobile Robot Lab Perth WA 6907 Australia

Parallaxis-III is an architecture-independent data parallel programming language based on Modula-2. It has been designed for teaching data parallel concepts and is in use at a large number of institutions. Compilers exist for data parallel systems, as well as for a sequential simulation system. A data parallel graphics debugger allows efficient source level analysis for parallel programs.

关键词： data parallel virtual architecture virtual processors parallel debugger data visualizer traffic simulation

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Celerity Hardware Implementation of the AES with data parallel and Pipelining Architecture inside the Round Function

Celerity Hardware Implementation of the AES with Data Parall...

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12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Yang, Shouwen Li, Hui Zhang, Xiaotao Zhao, Gang Beijing Univ Chem Technol Informat Secur & Intelligent Comp Lab Beijing 100029 Peoples R China

ISBN: (纸本)9780769550220

Since it was accepted as the replacement of the data Encryption Standard (DES) and 3 DES by NIST in 2001, the AES has played a major role in various security-constrained applications. Many applications are power-saving, resource constrained and require high-speed. AES is precisely suitable for being implemented in both software and hardware applications. Hardware implementation of AES has the advantage of increased throughput and better security. On the basis of those facts, in this paper, different hardware architectures of AES have been presented and surveyed. And we present a way of data parallel to deal with the bulk data of plaintext or cipertext, which brings lower clock cycles and increased working frequencies. Pipelining architecture inside the round function also contributed a lot to the promotion of data throughput. Moreover, the key schedule algorithm is pipelined to get the speedup, and the S-boxes which are based on look-up tables (LUTs) could be area-efficient. By conducting ALTERA FPGA realization and ModelSim simulation, we analyze the performance relating to the Slice registers, gate-level netlists, memory, Slice LUTs and so on.

关键词： AES data parallel Round Function Pipelining High-throughput

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Energy Management via PI Control for data parallel Applications with Throughput Constraints 25

Energy Management via PI Control for Data Parallel Applicati...

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25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

作者： Molnos, Anca Lombardi, Warody Puschini, Diego Mottin, Julien Lesecq, Suzanne Tonda, Arnaud Univ Grenoble Alpes Grenoble France CEA LETI Grenoble France

ISBN: (纸本)9781467394192

This paper presents a new proportional-integral (PI) controller that sets the operating point of computing tiles in a system on chip (SoC). We address data-parallel applications with throughput constraints. The controller settings are investigated for application configurations with different QoS levels and different buffer sizes. The control method is evaluated on a test chip with four tiles executing a realistic HMAX object recognition application. Experimental results suggest that the proposed controller outperforms the state-of-the-art results: it attains, on average, 25% less number of frequency switches and has slightly higher energy savings. The reduction in number of frequency switches is important because it decreases the involved overhead. In addition, the PI controller meets the throughput constraint in cases where other approaches fail.

关键词： PI control data parallel Energy management test chip Control Methods Throughput controller settings Workstations Tile energy saving Switches

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