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Area-efficient min-sum decoder design for high-rate quasi-cyclic low-density parity-check codes in magnetic recording

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IEEE TRANSACTIONS ON MAGNETICS 2007年第12期43卷 4117-4122页

作者： Zhong, Hao Xu, Wei Xie, Ningde Zhang, Tong Rensselaer Polytech Inst Troy NY 12180 USA LSI Corp San Jose CA 95134 USA

We report a silicon area efficient method for designing a quasi-cyclic (QC) low-density parity-check (LDPC) code decoder. Our design method is geared to magnetic recording that demands high code rate and very high decoding throughput under stringent silicon cost constraints. The key to designing the decoder is to transform the conventional formulation of the min-sum decoding algorithm in such a way that we can readily develop a hardware architecture with several desirable features: 1) silicon area saving potential inherent in the min-sum algorithm for high-rate codes can be fully exploited;2) the decoder circuit critical path may be greatly reduced;and 3) check node processing and variable node processing can operate concurrently. For the purpose of demonstration, we designed application-specific integrated circuit decoders for four rate-8/9 regular-(4, 36) QC-LDPC codes that contain 512-byte, 1024-byte, 2048-byte, and 4096-byte user data per codeword, respectively. Synthesis results show that our design method can meet the beyond-2 Gb/s throughput requirement in future magnetic recording at minimal silicon area cost.

关键词： decoder low-density parity-check (LDPC) min-sum algorithm very large scale integration (VLSI)

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Low-Power System Design for MPEG-2/4 AAC Audio decoder Using Pure ASIC Approach

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2009年第1期56卷 144-155页

作者： Tsai, Tsung-Han Liu, Chun-Nan Natl Cent Univ Dept Elect Engn Jhongli 32001 Taiwan

This paper presents an implementation of a low-power and pure-hardware advanced-audio-coding (AAC) audio decoder system. Based on the characteristics of each decoding block, the AAC system is partitioned into four separate modules. For low-power and low-complexity considerations, architectural- and algorithmic-level approaches are adopted in both individual modules and whole system. In parallel PLA-based codeword decoder, we achieve a constant output rate of Huffman decoding in 2.5 cycles for the worst case, and memory usage is decreased compared to that in the binary-tree memory-based method. In reduced lookup table inverse quantizer, a table lookup with interpolation scheme is adopted which reduces the size of the lookup table from 8192 to 256. In hardware-shared signal processor, we use a hardware-sharing technique which integrates several similar blocks into a common hardware to reduce cost and enhance hardware utilization. In fully pipelined filterbank, a fast algorithm decreases the numbers of multiplication and addition largely to factors of 24 and 144 for the short and long blocks, respectively. A corresponding hardware for filterbank processing is proposed with fully pipelined architecture. Referring to stereo processing, a single hardware is shared for the channel pairs with low-cost consideration. The hardware operations of each module are well scheduled with high utilization of pipeline, and furthermore, the parallel processing among blocks is Joined to increase efficiency. A 48% power savings can be reached by using the pipeline and parallel techniques of the channel pair. The proposed AAC decoder is realized in UMC 0.18-mu m 1P6M technology and is operated at only 3 MHz in the worst case. The power dissipation is only 2.45 mW at the sampling frequency of 44.1 kHz.

关键词： Advanced audio coding (AAC) audio decoder low power system

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Implementation of a Real-Time Versatile Video Coding decoder Based on VVdeC Over an Embedded Multicore Platform

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2023年第1期69卷 98-108页

作者： Saha, Anup Chavarrias, Miguel Aranda, Victor Garrido, Matias J. Pescador, Fernando Univ Politecn Madrid CITSEM Madrid 28031 Spain

The current state-of-the-art video coding standard versatile video coding (VVC) offers 50% bit rate savings over its predecessor high efficiency video coding (HEVC) while maintaining the same quality at the cost of a significant increase in the computational complexity. In this work, an Embedded General Purpose Processor (EGPP) with Single Instruction Multiple Data (SIMD) optimisations suite was used to accelerate an open-source software decoder for achieving real-time decoding over an embedded multi-core platform with 8 cores. The decoding speedup has been analyzed with different number of threads/cores, showing that performance increases linearly. This suggests that multi-core based performance for this solution did not reach the saturation point with 8 cores and more parallelism is possible using a higher number of cores. Thanks to the optimization process, x2 and x2.4 speedups have been obtained in the decoding time for All Intra and Random Access sequences, respectively. With these results, real-time decoding is achieved for High Definition (HD) sequences. The implementation of a real-time VVC decoder for a low resources embedded platform is the main contribution of this research.

关键词： Decoding Real-time systems Optimization Standards Encoding Streaming media Multicore processing decoder embedded systems H.266 multicore real-time SIMD VVC

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A 2-to-4 decoder switch in SiGe/Si multimode interference

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OPTICS EXPRESS 2006年第7期14卷 2671-2678页

作者： Chen, ZW Li, ZJ Li, BJ Sun Yat Sen Univ State Key Lab Optoelect Mat & Technol Inst Optoelect & Funct Composite Mat Guangzhou 510275 Peoples R China

Based on multimode interference principle and free-carrier plasma dispersion effect, a SiGe/Si 2-to-4 decoder switch is proposed and simulated. The decoder switch consists of two input single-mode ridge waveguides, a multimode interference section, and four output single-mode ridge waveguides. In the multimode interference section, two index-modulation regions are introduced. Design principle of the decoder switch is described and the device characteristics are demonstrated theoretically by beam propagation method. Simulated results show that the insertion loss of the decoder switch is less than 0.36 dB and the crosstalk is less than -19.7 dB. The device can divert input optical signals to any one of the four output waveguides when a forward bias voltage is applied to the two index-modulation regions. (c) 2006 Optical Society of America

关键词： .forward consists introduced Crosstalk simulated single-mode decoder insertion input optical multimode interference principle plasma dispersion indexmodulation output waveguides

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An Efficient LDPC decoder Architecture with a High-Performance Decoding Algorithm

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IEICE TRANSACTIONS ON COMMUNICATIONS 2010年第11期E93B卷 2980-2989页

作者： Hung, Jui-Hui Chen, Sau-Gee Natl Chiao Tung Univ Inst Elect Hsinchu 300 Taiwan

In this work a high performance LDPC decoder architecture is presented It is a partially parallel architecture for low complexity consideration In order to eliminate the idling time and hardware complexity in conventional partially parallel decoders the decoding process decoder architecture and memory structure are optimized Particularly the parity check matrix is optimally partitioned into four unequal sub matrices that lead to high efficiency in hardware sharing As a result it can handle two different codewords simultaneously with 100% hard ware utilization Furthermore for minimizing the performance loss due to round off errors in fixed point implementations the well known mod died min sum decoding algorithm is enhanced by our recently proposed high performance CMVP decoding algorithm Overall the proposed de coder has high throughput low complexity and good BER performances In the circuit implementation example of the (576 288) parity check matrix for IEEE 802 16e standard the decoder achieves a data rate of 5 5 Gbps assuming 10 decoding iterations and 7 quantization bits with a small area of 653K gates based on UMC 90 nm process technology

关键词： channel coding LDPC decoder algorithm hardware

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An efficient automated image caption generation by the encoder decoder model

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MULTIMEDIA TOOLS AND APPLICATIONS 2024年第25期83卷 66175-66200页

作者： Ansari, Khustar Srivastava, Priyanka Sarala Birla Univ Ranchi 835103 Jharkhand India BIT Sindri Dhanbad Dept CSE Sindri 828123 Jharkhand India

Image caption generation is becoming one of the hot research topics and attracts various researchers. It is a complex process because it utilizes both NLP (natural language processing) and computer vision approaches for generating the tasks. A range of strategies are available for image captioning that connect the visual material with everyday language, such as explaining images with textual descriptions. Pre-trained classification networks like CNN and RNN-based neural network models are used in the literature to encrypt visual data. Even though various literature works have analyzed outstanding image caption techniques, they still lack in providing better performance for diverse databases. To overcome such issues, this research work presents an automated optimization deep learning model for image caption generation. Initially, the input image is pre-processed, and then the encoder decoder-based structure is utilized for extracting the visual features and caption generation. On the encoder side, the pre-trained ResNet 101 (residual network) is used to extract the visual features, and the SA- Bi-LSTM (self-attention with bi-directional Long Short-Term Memory) is used to generate the caption on the decoder side. In addition, an optimization model CA (Chimp algorithm) is used to improve detection performance in caption generation. The proposed encoder-decoder model is tested on benchmark datasets like Flickr8k, Flickr30k and COCO. Further, this model attained better BLEU and ribes scores of 0.8595 and 0.3531 on the Flickr8k dataset. Thus, the proposed SA-BiLSTM model achieved a significant performance in image caption generation.

关键词： Chimp Algorithm Deep Learning Models decoder Encoder Image Caption Generation Visual Features

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SegNet: A Deep Convolutional Encoder-decoder Architecture for Image Segmentation

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IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE 2017年第12期39卷 2481-2495页

作者： Badrinarayanan, Vijay Kendall, Alex Cipolla, Roberto Univ Cambridge Dept Engn Machine Intelligence Lab Cambridge CB2 1TN England

We present a novel and practical deep fully convolutional neural network architecture for semantic pixel-wise segmentation termed SegNet. This core trainable segmentation engine consists of an encoder network, a corresponding decoder network followed by a pixel-wise classification layer. The architecture of the encoder network is topologically identical to the 13 convolutional layers in the VGG16 network [1]. The role of the decoder network is to map the low resolution encoder feature maps to full input resolution feature maps for pixel-wise classification. The novelty of SegNet lies is in the manner in which the decoder upsamples its lower resolution input feature map(s). Specifically, the decoder uses pooling indices computed in the max-pooling step of the corresponding encoder to perform non-linear upsampling. This eliminates the need for learning to upsample. The upsampled maps are sparse and are then convolved with trainable filters to produce dense feature maps. We compare our proposed architecture with the widely adopted FCN [2] and also with the well known DeepLab-LargeFOV [3], DeconvNet [4] architectures. This comparison reveals the memory versus accuracy trade-off involved in achieving good segmentation performance. SegNet was primarily motivated by scene understanding applications. Hence, it is designed to be efficient both in terms of memory and computational time during inference. It is also significantly smaller in the number of trainable parameters than other competing architectures and can be trained end-to-end using stochastic gradient descent. We also performed a controlled benchmark of SegNet and other architectures on both road scenes and SUN RGB-D indoor scene segmentation tasks. These quantitative assessments show that SegNet provides good performance with competitive inference time and most efficient inference memory-wise as compared to other architectures. We also provide a Caffe implementation of SegNet and a web demo at http://***

关键词： Deep convolutional neural networks semantic pixel-wise segmentation indoor scenes road scenes encoder decoder pooling upsampling

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EDRNet: Encoder-decoder Residual Network for Salient Object Detection of Strip Steel Surface Defects

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2020年第12期69卷 9709-9719页

作者： Song, Guorong Song, Kechen Yan, Yunhui Northeastern Univ Sch Mech Engn & Automat Shenyang 110819 Peoples R China Northeastern Univ Minist Educ China Key Lab Vibrat & Control Aeroprop Syst Shenyang 110819 Peoples R China

It is still a challenging task to detect the surface defects of strip steel due to its complex variations, including variable defect types, cluttered background, low contrast, and noise interference. The existing detection methods cannot effectively segment the defect objects from complex background and have poor real-time performance. To address these issues, we propose a novel saliency detection method based on Encoder-decoder Residual network (EDRNet). In the encoder stage, we use a fully convolutional neural network to extract rich multilevel defect features and fuse the attention mechanism to accelerate the convergence of the model. Then in the decoder stage, we adopt the channels weighted block (CWB) and the residual decoder block (RDB) alternatively to integrate the spatial features of shallower layers and semantic features of deep layers and recover the predicted spatial saliency values step by step. Finally, we design the residual refinement structure with 1D filters (RRS_1D) to further optimize the coarse saliency map. Compared with the existing saliency detection methods, the deeply supervised EDRNet can accurately segment the complete defect objects with well-defined boundary and effectively filter out irrelevant background noise. The extensive experimental results prove that our method is consistently superior to the state-of-the-art methods with large margins and strong robustness, and the detection efficiency is at over 27 fps on a single GPU.

关键词： Feature extraction Saliency detection Decoding Residual neural networks Strips Steel Semantics Encoder– decoder residual refinement structure salient object detection surface defects

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High-performance Syndrome-based SD-BCH decoder Architecture using Hard-decision Kernel

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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2018年第6期18卷 694-703页

作者： Kim, Taesung Lee, Hanho Inha Univ Dept Informat & Commun Engn Incheon 22212 South Korea

This paper proposes a high-performance, low-complexity, soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and its efficient design techniques. The proposed SD-BCH decoder not only uses the test syndrome computation, but also non-iteration processes. The proposed (1020, 990) SD-BCH decoder achieves a 0.75 dB higher coding gain compared to the (1020, 990) hard-decision BCH (HD-BCH) decoder. The proposed SD-BCH decoder was designed and implemented using the 65-nm CMOS technology. The synthesis results show that the proposed SD-BCH decoder architecture with serial structure (P = 1) has 24.7K gate count, which leads to a 69% reduction in hardware complexity compared to the previous SD-BCH decoder architecture.

关键词： BCH codes soft-decision decoding decoder modified step-by-step algorithm

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A QFHD 30-frames/s HEVC decoder Design

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2016年第4期26卷 724-735页

作者： Chiang, Pai-Tse Ting, Yi-Ching Chen, Hsuan-Ku Jou, Shiau-Yu Chen, I-Wen Fang, Hang-Chiu Chang, Tian-Sheuan Realtek Semicond Corp Hsinchu 300 Taiwan PixArt Hsinchu Taiwan Elan Microelect Corp Hsinchu 30076 Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan

The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variable-size coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the 64x64 block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by 16 x 16 block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a 4x4 block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported 4096x2160

关键词： decoder High Efficiency Video Coding (HEVC) very-large-scale integration (VLSI) implementation

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