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14th Biennial Baltic Electronic Conference (BEC)

作者： Knudsen, Bjarke Gosvig Jensen, Morten Birklykke, Alex Koch, Peter Christiansen, Johan Laursen, Karl Alminde, Lars Le Moullec, Yannick Aalborg Univ Dept Elect Syst Aalborg Denmark Gomspace ApS Aalborg Denmark Tallinn Univ Technol TJ Seebeck Dept Elect Tallinn Estonia

ISBN: (纸本)9781467395397

ADS-B is increasingly used for air traffic control in areas covered by terrestrial receivers;however, its limited range makes it unsuitable for other areas such as the oceans. To overcome this limitation, it has been proposed to receive ADS-B signals from low earth orbit nano-satellites and relay them to the terrestrial receivers. This paper gives an overview of the GATOSS mission and of its highly-sensitive ADS-B software-defined radio receiver payload. Details of the design and implementation of the receiver's decoder are introduced. The first real-life, space-based results show that ADS-B signals are indeed successfully received in space and retransmitted to a terrestrial station by the GATOSS nano-satellite orbiting at 700+ km altitudes, thus showing that GATOSS is capable of tracking flights, including transoceanic ones, from space.

关键词： air traffic control artificial satellites ADS-B ADS-B signals ADS-B software defined radio receiver GATOSS mission GATOSS nano-satellite decoder implementation low earth orbit nanosatellites terrestrial receivers transoceanic ones Aircraft Databases Decoding Receivers Satellite broadcasting Satellites Synchronization Air Traffic Control Satellite broadcasting Receivers artificial satellite satellites Aircraft DECODING Database decoders

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Pipeline processing in low-density parity-check codes hardware decoder

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BULLETIN OF THE POLISH ACADEMY OF SCIENCES-TECHNICAL SCIENCES 2011年第2期59卷 149-155页

作者： Sulek, W. Silesian Tech Univ Inst Elect PL-44100 Gliwice Poland

Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

关键词： channel coding LDPC codes iterative decoding decoder implementation pipelined processing

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Capacity-Approaching Protograph Codes

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 2009年第6期27卷 876-888页

作者： Divsalar, Dariush Dolinar, Sam Jones, Christopher R. Andrews, Kenneth CALTECH Jet Prop Lab Pasadena CA 91109 USA

This paper discusses construction of protograph-based low-density parity-check (LDPC) codes. Emphasis is placed on protograph ensembles whose typical minimum distance grows linearly with block size. Asymptotic performance analysis for both weight enumeration and iterative decoding threshold determination is provided and applied to a series of code constructions. Construction techniques that yield both low thresholds and linear minimum distance growth are introduced by way of example throughout. The paper also examines implementation strategies for high throughput decoding derived from first principles of belief propagation on bipartite graphs.

关键词： Protograph codes LDPC codes weight enumeration iterative decoding threshold rate-compatible codes decoder implementation

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implementation aspects of LDPC convolutional codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2008年第7期56卷 1060-1069页

作者： Pusane, Ali Emre Feltstroem, Alberto Jimnez Sridharan, Arvind Lentmaier, Michael Zigangirov, Kamil Sh. Costello, Daniel J., Jr. Univ Notre Dame Dept Elect Engn Notre Dame IN 46556 USA DS2 Design Syst Silicon Valencia Spain

Potentially large storage requirements and long initial decoding delays are two practical issues related to the decoding of low-density parity-check (LDPC) convolutional codes using a continuous pipeline decoder architecture. In this paper, we propose several reduced complexity decoding strategies to lessen the storage requirements and the initial decoding delay without significant loss in performance. We also provide bit error rate comparisons of LDPC block and LDPC convolutional codes under equal processor (hardware) complexity and equal decoding delay assumptions. A partial syndrome encoder realization for LDPC convolutional codes is also proposed and analyzed. We construct terminated LDPC convolutional codes that are suitable for block transmission over a wide range of frame lengths. Simulation results show that, for terminated LDPC convolutional codes of sufficiently large memory, performance can be improved by increasing the density of the syndrome former matrix.

关键词： low-density parity-check codes convolutional codes iterative decoding message-passing decoding decoder implementation

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Ultra-High-Throughput EMS NB-LDPC decoder with Full-Parallel Node Processing

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2022年第10期94卷 1031-1045页

作者： Harb, Hassan Al Ghouwayel, Ali Chamas Conde-Canencia, Laura Marchand, Cedric Boutillon, Emmanuel Univ Bretagne Sud Lab STICC UMR 6285 Lorient France Lebanese Int Univ LIU CCE Dept Beirut Lebanon Ecole Polytech Fed Lausanne Lausanne Switzerland

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10(-3).

关键词： Channel coding decoder implementation ASIC non-binary LDPC Min-Sum Parity check

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Non-binary LDPC decoders Design for Maximizing Throughput of an FPGA implementation

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2016年第11期35卷 4060-4080页

作者： Sulek, Wojciech Silesian Tech Univ Akad 16 PL-44100 Gliwice Poland

Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless computation units. In this article, we present a different decoder design approach that is specifically intended for an FPGA implementation. We reformulate the mixed-domain FFT-BP decoding algorithm and develop a decoder architecture that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA, thus making use of all the types of FPGA resources. Then, the throughput limit achievable in a single FPGA by the proposed decoder is significantly increased. We also consider another important optimization of the decoder implementation, mainly an efficient realization of the permutation units and an approximated evaluation of the nonlinear functions of messages. Another motivation is to make the decoder easily scalable for FPGA devices of different sizes. To achieve this goal, the configurable semi-parallel decoder architecture is applied operating for the structured subclass of codes.

关键词： Error control coding Low-density parity-check codes Non-binary codes LDPC decoding decoder implementation

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Generic description and synthesis of LDPC decoders

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IEEE TRANSACTIONS ON COMMUNICATIONS 2007年第11期55卷 2084-2091页

作者： Guilloud, Frederic Boutillon, Emmanuel Tousch, Jacky Danger, Jean-Luc Ecole Natl Super Telecommun Bretagne Dept Signal Commun GET Brest 3 France Univ Bretagne Sud LESTER Lorient France TurboConcept SAS Plouzane France Ecole Natl Supr Telecommun F-75013 Paris France

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for non-flooding schedules is also given.

关键词： binary low-density parity-check (LDPC) codes decoder implementation iterative decoding VLSI

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Hardware-Oriented Turbo-Product Codes decoder Architecture 9

Hardware-Oriented Turbo-Product Codes Decoder Architecture

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9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems - Technology and Applications (IDAACS)

作者： Krainyk, Yaroslav Perov, Vladyslav Musiyenko, Maksym Davydenko, Yevhen Petro Mohyla Black Sea Natl Univ Dept Comp Engn Mykolaiv Ukraine

ISBN: (纸本)9781538606971

Model of Turbo-Product Codes decoder architecture and method for construction of Turbo-Product Codes decoder are proposed in the paper. The model describes decoder functioning taking into account limitations of hardware platform and proposes re-use of components in the decoding process. The method provides set of steps for decoder implementation. Field-Programmable Gate Arrays circuits are selected as hardware platform. Implemented decoder demonstrates high throughput and can decode codes that consist of Hamming codes with different codeword length that can be configured "on-the-fly".

关键词： TPC-decoder hardware utilization decoder architecture memory blocks decoder implementation

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