Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

作     者：Harb, Hassan Al Ghouwayel, Ali Chamas Conde-Canencia, Laura Marchand, Cedric Boutillon, Emmanuel 

作者机构：Univ Bretagne Sud Lab STICC UMR 6285 Lorient France Lebanese Int Univ LIU CCE Dept Beirut Lebanon Ecole Polytech Fed Lausanne Lausanne Switzerland 

出 版 物：《JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY》 (超大规模集成电路信号处理系统杂志)

年 卷 期：2022年第94卷第10期

页      面：1031-1045页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：EPFL Lausanne 

主　　题：Channel coding Decoder implementation ASIC non-binary LDPC Min-Sum Parity check 

摘      要：This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10(-3).