作者：
Wu, PengMIT AI Lab
545 Technology Sq. Rm833 CambridgeMA02139 United States
This paper presents an implemented system for modifying digital circuit designs to enhance testability. The key contributions of the work are: (1) setting design for testability in the context of test generation, (2) ...
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This presentation will discuss the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in ...
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This presentation will discuss the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs. These techniques include the three main areas of design for testability, 1) Ad Hoc approaches; 2) Structured approaches; and, 3) Self Test/Built-in Test approaches.
In an attempt to curtail the almost exponential growth in testing cost as circuit complexity increases, attention has focussed over the past decade on design for testability (DFT). Although DFT techniques reduce the t...
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In an attempt to curtail the almost exponential growth in testing cost as circuit complexity increases, attention has focussed over the past decade on design for testability (DFT). Although DFT techniques reduce the testing cost there is a penalty to be paid in terms of the overheads incurred through their use. The paper first presents several recently evolved hybrid techniques that combine several DFT techniques with the objective of maximizing the advantages of each method whilst minimizing their overheads. It has been predicted that, as a result of the decrease in device size through the improvements in fabrication technology, the incidence of intermittent faults will increase. Current test strategies are not generally suitable for detecting this type of fault, and the paper discusses the application of concurrent circuit testing techniques, employing information redundancy, to the problem. The vast number of DFT techniques available, each with its own advantages and disadvantages, means that the designer faces a formidable task in selecting the best technique for a particular circuit. Several expert systems developed to analyse the circuit and suggest the most appropriate technique are presented. This approach has been developed further by integrating the expert system into a silicon compiler environment which ensures that the circuit is testable by virtue of its construction.
A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and...
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A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered.< >
The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possi...
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The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans.< >
Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This pa...
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Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.
Clearly, in today's complex systems, hardware and software approaches to DFT must work together to achieve a successful overall solution. The authors investigate existing and new concepts that may lead to a single...
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Clearly, in today's complex systems, hardware and software approaches to DFT must work together to achieve a successful overall solution. The authors investigate existing and new concepts that may lead to a single design for test strategy in the future.
Testable designs for the TX1 1 , a 32-bit microprocessor based on the TRON architecture 2 , are described. Clear testing strategies have been developed, resulting in three testable design approaches implemented in an ...
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Testable designs for the TX1 1 , a 32-bit microprocessor based on the TRON architecture 2 , are described. Clear testing strategies have been developed, resulting in three testable design approaches implemented in an optimized form. Logic function test is composed of scan test and self test. Their efficiency is enhanced greatly by the use of the bus structure and microinstruction set of the TX1. Fault coverage of over 90% is achieved with a short testing time (a few seconds) and a small increase in chip area (4.2%). design verification is done via scan test and ‘macroblock’ test. The latter can test important manually designed hardware blocks directly, independent of the complicated decode and control logic. The increase in chip area is only 0.4%. Macroblock testing can give useful information for making refinements in the early phases of development.
Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllab...
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Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.
作者：
Ihs, HDufaza, CUMR 9928 CNRS
Laboratoire d'Informatique de Robotique et de Micro-électroniquede Montpellier Université Montpellier II Montpellier Cedex 5 France
The authors present a design for testability (DFT) technique for switched-capacitor circuits. The principle is to reconfigure the SC circuit so that it realises a cascade of DC voltage amplifiers in which all capacito...
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The authors present a design for testability (DFT) technique for switched-capacitor circuits. The principle is to reconfigure the SC circuit so that it realises a cascade of DC voltage amplifiers in which all capacitors are represented in a simple form. Then, the transfer function becomes a product of the ratio of two capacitors and the sensibility of the DC gain to each capacitor is close to unity. Consequently, a simple test with partial diagnosis is realised with some DC voltage stimuli and gives an accurate test result at the output of the last voltage amplifier.
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