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Multi-rate Real Time Hybrid Simulation operated on a flexible LabVIEW real-time platform

ENGINEERING STRUCTURES 2021年 239卷 112308-112308页

作者： Waldbjoern, P. Jacob Maghareh, Amin Ou, Ge Dyke, J. Shirley Stang, Henrik Tech Univ Denmark Dept Mech Engn Niels Koppels 404 DK-2800 Lyngby Denmark Tech Univ Denmark Dept Civil Engn Brovej 118 DK-2800 Lyngby Denmark Purdue Univ Lyles Sch Civil Engn 550 Stadium Mall Dr W Lafayette IN 47907 USA

This paper presents a real-time hybrid simulation (RTHS) strategy where the numerical and experimental substructures are executed at two different rates to optimize computational resources while maintaining an effective actuator control. The concept is referred to here as multi-rate real-time hybrid simulation (mrRTHS), and this approach is intended to enable low-cost RTHS by facilitating testing in the case of limited computational resources. Operated on a Laboratory Virtual Engineering Workshop (LabVIEW) real-time target, the mrRTHS concept is demonstrated through both a single- and multipledegree-of-freedom (SDOF) and (MDOF) mass-springdamper system. The numerical substructure generates a displacement signal with a coarse time step of Delta t. Using the current and three previous displacement data points, a finer control signal is defined with a time step of delta t, using a third-order polynomial algorithm referred to here as the polynomial fitting extrapolator. Both the numerical substructure and polynomial fitting extrapolator is executed with a sampling rate of Delta t by an on-board single-core processor-referred to here as the digital signal processor (DSP). Through a field-programmable gate array (FPGA) the control signal is compensated and transmitted to the transfer system through an I/O module with a sampling rate of 1 kHz (i.e. delta t = 0.001 sec). The ratio between Delta t and delta t are an integer-referred to here as the execution ratio. For an execution ratio of 1:5 and 1:10 the system performance is evaluated against a numerical model of the emulated structure-referred to here as the reference structure. For both the SDOF and MDOF system, a good correlation between the mrRTHS and reference is achieved with execution ratios of 1:5 and 1:10. When changing the execution ratio from 1:5 to 1:10, approximately 50% reduction of the required computational resources on the DSP is achieved.

关键词： Real-time hybrid simulation Hardware-in-the-loop Performance evaluation Experimental substructure Numerical substructure field programmable gate array

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Multi-Partitioned Software Defined Radio Transceiver Based on Dynamic Partial Reconfiguration 52

Multi-Partitioned Software Defined Radio Transceiver Based o...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Hosny, Sherif Elnader, Eslam Gamal, Mostafa Hussien, Abdelrhman Mostafa, Hassan Mentor Graph Corp Wilsonville OR 97070 USA Cairo Univ Elect & Commun Engn Dept Cairo Egypt Univ Sci & Technol Zewail City Sci & Technol Nanotechnol & Nanoelect Program October Gardens Giza 12578 Egypt

ISBN: (纸本)9781728133201

Dynamic Partial Reconfiguration (DPR) proved itself for the implementation of multi-standard Software Defined Radio (SDR). Over the past few years, wireless communication standards witnessed great and rapid evolution. The market is always acquiring higher data rates and more special services. This leads to increase of design complexity, area, and power consumption. Deploying DPR technology on field programmable gate arrays (FPGAs) made it feasible to design and manufacture all wireless communications standards on the same hardware. Loading each standard on demand reduces area and power consumption. This work implements SDR transceiver system for five wireless communication standards: Bluetooth, Wi-Fi, 2G, 3G, and LTE on Zynq-7000 evaluation kit. A new partitioning approach is deployed to achieve best performance for all transceivers. The new approach proves its ability to reduce the allocated area and power consumption for all chains. Power reduction for 2G and Bluetooth is 98.43%, for 3G and Wi-Fi is 79.69%, for LTE is 50.09% compared with no DPR approach.

关键词： Software Defined Radio Dynamic Partial Reconfiguration field programmable gate array and System on Chip

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An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2021年第4期30卷

作者： Iqbal, Muhammad Mazher Parvez, Husain Hussain, Fasahat Rashid, Muhammad Karachi Inst Econ & Technol Karachi 75190 Pakistan Digitek Engn Karachi Pakistan Umm Al Qura Univ Coll Comp & Informat Syst Comp Engn Dept Mecca Saudi Arabia

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF++. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF++. It is found through experimental results that an ASIF++ is 4-9% area-efficient and requires 36% lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2-5 circuits. It also achieves 34-53% area saving as compared to a traditional FPGA.

关键词： Application specific FPGA reconfigurable ASIC NPN SRAM-Table sharing field programmable gate array reconfiguration overheads

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FPGA-Based Cost-Effective and Resource Optimized Solution of Predictive Direct Current Control for Power Converters

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ENERGIES 2021年第22期14卷 7669页

作者： Sankar, Deepa Syamala, Lakshmi Ayyappan, Babu Chembathu Kallarackal, Mathew Cochin Univ Sci & Technol Div Elect Engn Ernakulam 682022 India Mar Athanasius Coll Engn Dept Elect & Commun Engn Kothamangalam 686666 India

Recent advances in power converter applications with highly demanding control goals require the efficient implementation of superior control strategies. However, the real-time application of such control strategies demands high computational power that necessitates efficient digital controllers like field programmable gate array (FPGA). The inherent parallelism offered by FPGAs minimizes the execution time and exhibits an excellent cost-performance trade-off. In addition, rapid advancements in FPGA technology with a broad portfolio of intellectual property (IP) cores, design tools, and robust embedded processors resulted in a design paradigm shift. This article proposes a low-cost solution for the resource-optimized implementation of dynamic, highly accurate, and computationally intensive finite state-predictive direct current control (FS-PDCC). The challenges for implementing complex control algorithms for power converters are discussed in detail, and the control is implemented in Intel's low-cost non-volatile FPGA-MAX (R) 10. An efficient design methodology using finite state machine (FSM) is adopted to achieve time/resource-efficient implementation. The parallel and pipelined architecture of FPGA provides better resource utilization with high execution speed. The experimental results prove the efficiency of FPGA-based cost-effective solutions that offer superior performance with better output quality.

关键词： field programmable gate array intellectual property core finite control set model predictive control finite state machine resource optimization voltage source inverter analog to digital converter

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A Fully FPGA Implementation of SVPWM for Three-phase Inverters without External Reference Signals

A Fully FPGA Implementation of SVPWM for Three-phase Inverte...

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20th IEEE International Conference on Environment and Electrical Engineering (EEEIC) / 4th IEEE Industrial and Commercial Power Systems Europe Conference (I and CPS Europe)

作者： Donisi, Andrea Di Benedetto, Luigi Licciardo, Gian Domenico Rubino, Alfredo Piccirilli, Eduardo Lanzotti, Emilio Univ Salerno Dept Ind Engn Fisciano SA Italy Hitachi Rail STS ACC Gener Prod & Wayside Devices Naplo Italy

ISBN: (纸本)9781728174556

In this paper we propose a novel method to implement Space Vector Pulse Width Modulation algorithm in field programmable gate array hardware. It is based on storing pre-calculated and normalized dwell times in internal Look-Up Tables of FPGA and on the evaluation through FPGA of the effective dwell times, as function of the modulation index, and of the relative configurations of the power transistors. The input data is the modulation index, instead the switching frequency and the output frequency are defined when the normalized dwell times are calculated. This method permits to significantly reduce hardware resources and computational cost of the FPGA. Although it is proposed to drive three-phase motor in open-loop control, the modulation index can be linearly changed from the user in real-time so that a start-up ramp of the output voltage amplitude ca be performed, for example. The method is implemented on FPGA Artix7 from Xilinx, Inc. by using 420 LUT and 245 FF, which are, respectively, 2.2% and 0.59% of the overall resources, without requiring any Digital Signal Processing and BRAMs. Experimental results show the gate control signals of the power transistors to generate an output voltage at 50Hz with a start-up voltage ramp and a switching frequency of 9.75kHz.

关键词： Space Vector Pulse Width Modulation field programmable gate array Three-Phase Inverter Switching control DC/AC power converter

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Six-port Reflectometer with Kalman Filter Processing of Sensor Signals 15

Six-port Reflectometer with Kalman Filter Processing of Sens...

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15th International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET)

作者： Zaichenko, Olga Galkin, Pavlo Zaichenko, Nataliia Miroshnyk, Marina Kharkiv Natl Univ Radioelect Dept Design & Operat Elect Devices Kharkov Ukraine Ukrainian State Univ Railway Transport Dept Specialized Comp Syst Kharkov Ukraine

ISBN: (纸本)9781728155661

In modern microwave measurements the six-port reflectometers and receivers are used in telecommunications, radiolocation, medicine, Internet of things. The signal processing is based on the algorithms and models that using the redundant information and is aimed at accuracy improving and uncertainty reducing. The Kalman filter is proven to be helpful in signals with errors processing. There was proposed a finite state machine (FSM) with such states as prediction and update for Kalman filter algorithm and its simulation with the help of field programmable gate array (FPGA).

关键词： six-port reflectometer six-port receiver Kalman filter finite state machin field programmable gate array processing algorithm redundancy

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Frequency Division Control of Three-level APF Harmonic Based on FPGA 9

Frequency Division Control of Three-level APF Harmonic Based...

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IEEE 9th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia)

作者： Zhou Jing-hua Wang Chen Zhang Xin-lei Zhang Xiao-wei North China Univ Technol Frequency Convers Technol Beijing Engn Res Ctr Beijing Peoples R China

ISBN: (纸本)9781728153018

An active power filter (APF) harmonic current frequency division compensation digital control system is built with a field programmable gate array (FPGA) as the core processor. The FPGA has an extremely high parallel execution mode, and each harmonic calculation module can be simultaneously performed, thereby solving the problems of limited harmonic number and poor compensation effect of traditional serial execution mode. Besides, FPGA can minimize the delay caused by calculation, make the digital control system have quasi-analog circuit characteristics, and significantly improve the real-time processing. The experiments are carried out on the three-level APF prototype, and the expected experimental results are achieved. The correctness of the harmonic frequency division control method of FPGA proposed in this paper is verified.

关键词： field programmable gate array Active Power Filter digital control system Harmonic Current Frequency Division Control

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HARDWARE ACCELERATOR: IMPLEMENTATION OF CNN ON FPGA FOR DIGIT RECOGNITION 24

HARDWARE ACCELERATOR: IMPLEMENTATION OF CNN ON FPGA FOR DIGI...

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24th International Symposium on VLSI Design and Test (VDAT)

作者： Choudhari, Onkar Chopade, Marisha Chopde, Sourabh Dabhadkar, Swarali Ingale, V Elect & Telecommun Coll Engn Pune Maharashtra India

ISBN: (纸本)9781728193694

Convolutional Neural Network (CNN) is a special kind of feed - forward Artificial Neural Network that is generally used for fast and accurate image recognition. This capability is highly required in the field of embedded systems for various applications. Embedded systems present a compelling need for a portable, low power and area - efficient hardware accelerator. Also, the large amount of processing needed by CNN demands dedicated and custom-built hardware implementations. The convolution part of CNN is a highly parallelized Digital Signal Processing (DSP) algorithm which makes it fit for field programmable gate array (FPGA) implementation as FPGAs have an incontestable ability to maximize parallelism. In this paper, we present the implementation of CNN on FPGA. We came up with a smaller version of LeNet - 5 with a parametric reduction of about 95% and having accuracy of 95.33% for the application of digit recognition. The complete modified architecture is implemented using Hardware Description Language - Verilog with the aim of improving the timing performance in the inference phase. The proposed work is compared with a software implementation on an 8th generation i5 processor using Keras. The results obtained clearly demarcate acceleration. The hardware architecture is designed to fit on Kintex - 7 xck325ttfg900-2l FPGA optimally. The obtained results can be easily extrapolated for an improved architecture showcasing four times more parallelism for FPGAs having more DSP slices (e.g. Virtex 7 series).

关键词： Convolutional Neural Network field programmable gate array Verilog acceleration

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FPGA implementation of collateral and sequence pre-processing modules for low power ECG denoising module

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Informatics in Medicine Unlocked 2022年 28卷

作者： Kirti Sohal, Harsh Jain, Shruti Department of Electronics and Communication Galgotias College of Engineering and Technology Greater Noida U.P India Department of Electronics and Communication Jaypee University of Information Technology Wakhnaghat Solan India

ECG signal recording easily suffers from interferences in the environment, such as patient movement, and position of electrodes. For primary diagnosis, doctors need noise-free ECG signals. This paper presents the hardware implementation of denoising of ECG signals using various types of linear windowing techniques and non-linear discrete wavelet transform (DWT) on the proposed architectures using FPGA. DWT has extensive usage in different image processing applications as image compression and information hiding. The simulation results obtained from various techniques and architectures are compared using MATLAB and XILINX VIVADO EDA tools. The performance evaluation of the proposed methodology is evaluated on the basis of resource utilization and on-chip power consumption on the different FPGA boards (Virtex, Kintex, and Zedboards) using VIVADO. From the simulation results, inference has been drawn that Haar wavelet consumes only 0.76% of LUTs, 5.03% of slice registers and 6.7% of DSPs in comparison with other wavelet and window techniques using Zedboard. The Haar wavelet based pre-processor design only consumes 136 mW of on-chip power. The proposed pre-processing module can be used in wearable and portable biomedical equipments. © 2021 The Authors

关键词： Baseline wander Electrocardiogram Electromyography field programmable gate array

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field programmable gate array implementation of a fault location system in transmission lines based on artificial neural networks

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IET GENERATION TRANSMISSION & DISTRIBUTION 2011年第2期5卷 191-198页

作者： Ezquerra, J. Valverde, V. Mazon, A. J. Zamora, I. Zamora, J. J. Univ Basque Country Elect & Telecommun Dept Fac Engn Bilbao Bilbao 48013 Spain Univ Basque Country Dept Elect Engn Fac Engn Bilbao Bilbao 48013 Spain

In the field of electrical engineering there are many areas where artificial neural networks (ANNs) are being applied. ANNs can be modelled and implemented by means of the execution of specific software in sequential computers. Nevertheless, if a real-time application wants to be developed, it is necessary to study how to use its massively parallel processing capacity by a specific electronic system. This study presents the methodology, the design and the field programmable gate array implementation process of a fault classification and location prototype for overhead transmission lines, based on ANNs.

关键词： Overhead power lines fault classification field programmable gate arrays Logic circuits Neural computing techniques power engineering computing sequential computers fault location artificial neural networks power transmission faults Logic and switching circuits field programmable gate array fault location system electrical engineering Power engineering computing power overhead lines neural nets overhead transmission lines

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