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Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第6期33卷 1715-1728页

作者： Sanjaya, Sahan Jayasena, Aruna Mishra, Prabhat Univ Florida Dept Comp & Informat Sci & Engn Gainesville FL 32611 USA

Power side-channel attacks are widely known for extracting information from data processed within a device while assuming that an attacker has physical access or the ability to modify the device. In this article, we introduce a novel side-channel vulnerability that leaks data-dependent power variations through physical layer supply voltage coupling (PSVC). Unlike traditional power side-channel attacks, the proposed vulnerability allows an adversary to mount an attack and extract information without modifying the device. In addition, unlike existing power-based remote attacks on field-programmable gate arrays (FPGAs), the PSVC vulnerability applies to both on-chip and on-board attacks. We assess the effectiveness of the PSVC vulnerability through three case studies, demonstrating several end-to-end attacks on general-purpose microcontrollers with varying adversary capabilities. These case studies provide evidence for the existence of the PSVC vulnerability, its applicability to on-chip as well as on-board side-channel attacks, and how it can eliminate the need for physical access to the target device, making it applicable to any off-the-shelf hardware. Our experiments also reveal that designing devices to operate at the lowest operational voltage significantly reduces the risk of PSVC side-channel vulnerability.

关键词： Couplings Side-channel attacks Silicon Power demand Data mining Substrates Information leakage Hardware field programmable gate arrays Performance evaluation security side-channel vulnerability supply voltage coupling

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Design and Implementation of FRM-Based Wideband Channelizer for Passive Detection and Jamming Integrated Processor

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Zhang, Wenxu Zhao, Xiaoqi Zhao, Zhongkai Luo, Kang Liu, Feiran Harbin Engn Univ Coll Informat & Commun Engn AVIC United Technol Ctr Electromagnet Spectrum Col Key Lab Adv Marine Commun & Informat TechnolMinis Harbin 150001 Heilongjiang Peoples R China Harbin Engn Univ Yantai Res Inst Yantai 264000 Peoples R China Harbin Engn Univ Coll Informat & Commun Engn Harbin 150001 Heilongjiang Peoples R China Wright State Univ Dept Elect Engn Dayton OH 45435 USA

In this paper, we propose a frequency response masking (FRM)-based wideband channelizer for passive detection and jamming integrated (PDJI) processor to achieve high sensitivity and the ability to simultaneously jam multiple signals. The FRM method is used to design the prototype filter with narrow transition bandwidth (NTB) in order to acquire low complexity. The prototype filter with NTB is decomposed into the polyphase filters of the channelized receiver and channelized transmitter structures by polyphase decomposition. A hardware circuit design of the PDJI processor based on radio frequency system on chip (RFSoC) is presented, which has 5-channel receiving and 1-channel transmitting capability. The proposed FRM-based wideband channelizer structure for PDJI processor is implemented on Xilinx Zynq UltraScale+ XCZU47DR chip. Experimental results demonstrate that, compared to the non-maximally decimated digital channelizer and generalized polyphase digital channelizer, the proposed FRM-based wideband channelizer offers 21.73% and 23.23% reduction in multiplier consumption, and 18.66% and 19.76% reduction in chip power respectively under single channel receiving and single channel transmitting conditions.

关键词： Wideband Jamming field programmable gate arrays Finite impulse response filters Filter banks Computational complexity Antenna arrays Hardware Sensitivity Receiving antennas Passive detection and jamming integrated wideband channelizer frequency response masking low complexity radio frequency system on chip

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On the Development of an RFSoC-Based Ultra-Fast Phasemeter With GHz Bandwidth

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Subrahmanya, Shreevathsa Chalathadka Darsow-Fromm, Christian Gerberding, Oliver Univ Hamburg Inst Expt Phys D-22761 Hamburg Germany

Precise measurements of the change in the frequency and phase of an electrical or optical signal play a key role in various branches of science and engineering. Tracking changing laser frequencies is especially demanding when the lasers themselves are noisy or if the frequencies rapidly change because they encode highly dynamic signals in, e.g., Doppler-ranging or dynamic cavity readout. Here, to address these and other possible applications, we report the development of a high signal bandwidth (>2 GHz) and high tracking bandwidth (2 MHz) multichannel phasemeter. The implementation utilizes an all-digital phase-locked loop (ADPLL) realized within the field programmable gate array (FPGA) part of a radio frequency system-on-chip (RFSoC), the programmable logic (PL). The benchmark level parameters of the phasemeter are obtained by operating the PL at its timing limits and introducing a novel multi-demodulation and phase accumulation scheme. We present performance measurements, discuss the role of the high tracking bandwidth for tracking highly dynamic signals, and demonstrate ultra-stable phase locking of a beat note between two widely tunable external cavity diode lasers. Within our implementation, we have included a direct measurement of the open-loop gain of the phase-locked loop (PLL) and an estimation of the residual phase error. These features are new in the field of FPGA-based phasemeter developments. We achieve a phase-noise floor in the sub-milli radian regime when comparing two signals, even for GHz frequencies, and demonstrate stable tracking of signals with a frequency change rate of 240 GHz/s.

关键词： Bandwidth Phase locked loops Frequency measurement Measurement by laser beam Table lookup Phase measurement Laser stability Laser noise Instruments field programmable gate arrays field programmable gate arrays (FPGAs) frequency measurement phase-locked loops (PLLs)

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Data Acquisition System for CEPC Vertex Detector Prototype

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 406-413页

作者： Xu, Chang Zhang, Hongyu Zhou, Jia Chen, Yiming Yan, Ziyue Liang, Zhijun Wu, Tianya Hu, Jun Wei, Wei Zhang, Ying Chinese Acad Sci Inst High Energy Phys Beijing 100049 Peoples R China Univ Chinese Acad Sci Sch Nucl Sci & Technol Beijing 100049 Peoples R China Beijing Res Inst Telemetry Beijing 100071 Peoples R China Nanchang Univ Sch Informat Engn Nanchang 330031 Peoples R China

In the proposed Circular Electron Positron Collider (CEPC), the silicon pixel vertex detector demands high spatial resolution, low power consumption, and minimal material budget, posing significant challenges in chip design and detector fabrication. TaichuPix series chips, based on complementary metal-oxide semiconductor technology, were specifically designed for the CEPC vertex detector. The first full-size engineering chips, TaichuPix-3, were utilized in the development of the vertex detector prototype. To test and investigate the performance of the chips and the prototype of the vertex detector in beam experiments, a dedicated data acquisition system was developed. Based on the JavaFx framework and programmed in Java, the system efficiently manages the electronics configuration, data collection, online data verification, and real-time monitoring of the detector prototype, while also providing a user-friendly graphical interface for run control. Laboratory tests and beam tests have validated the data acquisition system in terms of functionality and operational stability, confirming that it fully meets the experimental requirements of the silicon pixel vertex detector prototype.

关键词： Detectors Prototypes Data acquisition Software Readout electronics Silicon field programmable gate arrays Clocks Testing Logic Data acquisition system JavaFx framework silicon pixel vertex detector

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A High-Reliability, Non-CRP-Discard Arbiter PUF Based on Delay Difference Quantization

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第2期72卷 573-585页

作者： Wang, Yao Zhang, Guangyang Mei, Xue Gu, Chongyan Zhengzhou Univ Sch Elect & Informat Engn Zhengzhou 450001 Peoples R China Queens Univ Belfast Ctr Secure Informat Technol CSIT Belfast BT3 9DT North Ireland

As a lightweight hardware security primitive, physical unclonable functions (PUFs) can provide reliable identity authentication for the Internet of Things (IoT) devices with limited resources. Arbiter PUF (APUF) is one of the most well-known PUF circuits. However, its hardware implementation has poor reliability on field programmable gate arrays (FPGAs). This paper proposed a highly reliable APUF that uses a delay difference quantization strategy (DDQ-APUF). By adding multiple configurable delay units to the two symmetrical paths of the conventional APUF, the delay difference between the two symmetrical paths of APUF can be obtained by collecting the output of APUF under different delay configurations. Compared to conventional APUFs, DDQ-APUF does not use the arbitration result of signal transmission in two symmetric paths as its response, but rather uses the quantified delay difference between the two paths as its response. A tolerance threshold is adopted in the authentication to accommodate the variations in delay differences due to environmental changes. Moreover, the modeling attack resistance of DDQ-APUF is evaluated, and a strategy for improving this resistance by incorporating pseudo-XOR technique is proposed. The circuit was implemented on Xilinx Artix-7 FPGAs and the experimental results show that the reliability achieves 99.95 $\%$ with non-CRP-discard.

关键词： Delays Circuits Authentication Integrated circuit reliability field programmable gate arrays Error correction codes Physical unclonable function Nonvolatile memory Quantization (signal) Internet of Things DDQ-APUF FPGA IoTs security authentication

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A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第4期33卷 1042-1052页

作者： Xu, Chaolong Lv, Fangxu Lai, Mingche Qi, Xingyun Wang, Qiang Luo, Zhang Li, Shijie Zhang, Geng Natl Univ Def Technol Coll Comp Sci & Technol Changsha 410073 Peoples R China

To solve the high bit error rate (BER) problem of conventional 56-Gb/s nonreturn-to-zero (NRZ) transceivers under high-insertion loss (IL) channels, this study proposes a high-speed adaptive duobinary (DB) digital detector based on the feed-forward equalizer (FFE) and the maximum likelihood sequence detector (MLSD). In this detector, adaptive FFE is combined with channel characteristics to generate DB signals and complete equalization, thus extending the transmission bandwidth and eye height and allowing a larger sampling phase offset. The parallel MLSD is used to complete the detection and decoding of DB signals to reduce the BER. An adaptive algorithm is proposed to avoid the long convergence time of the conventional zero-forcing (ZF) algorithm applied to the DB detector, so that it can be applied to various bit rates and IL channels. In this study, the verification of this DB detector is accomplished at 56 Gb/s. The platform based on a 56-Gb/s analog front-end chip (AFEC) and field-programmable gate array (FPGA) proves that the detector can work well in 12-56 Gb/s and multiple IL channels. The BER was less than 2e-8 at 56 Gb/s on -42-dB channel loss at 28 GHz. The structure can be well used for higher rate transceivers, such as 112 Gb/s.

关键词： Optical signal processing Detectors Transceivers Equalizers Receivers Transmitters Bandwidth field programmable gate arrays Constellation diagram Bit error rate Duobinary (DB) feed-forward equalizer (FFE) field-programmable gate array (FPGA) maximum likelihood sequence detector (MLSD) nonreturn-to-zero (NRZ) zero-forcing (ZF) algorithm

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A Fully Reconfigurable Pipelined Architecture for FPGA-Based Parallel PRBS Test Pattern Generators

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 446-453页

作者： Zhu, Chengyang Song, Kezhu Zou, Dongwei Chen, Zhuo Univ Sci & Technol China Dept Modern Phys State Key Lab Particle Detect & Elect Hefei 230026 Peoples R China

Serial links are widely used for data transfer in data acquisition (DAQ) systems of high-energy physics (HEP) experiments. Pseudorandom binary sequences (PRBSs) based on linear feedback shift registers (LFSRs) are commonly used as test patterns for link error testing and characterization in communication systems based on serial links. This article presents a flexible architecture for field-programmable gate array (FPGA)-based PRBS generation with full reconfigurability and high throughput. The proposed architecture is highly scalable, with extensible parallel datapaths to meet the demands of increasing data rates of serial links. The architecture is designed to be fully parametric, allowing dynamic reconfiguration of all parameters at runtime with simple writes to configuration registers. The design is optimized for efficient FPGA implementation, where extensive pipelining is exploited to achieve optimal timing performance and scalability. A built-in bootstrap unit is incorporated to generate datapath control signals from input parameters and prefill the pipeline stages on a reconfiguration event. Furthermore, a general approach to converting an existing PRBS generator into a self-synchronizing checker is illustrated and applied to the proposed architecture where an additional checker extension unit is incorporated to allow operation as a PRBS checker. The proposed flexible architecture facilitates serial link error testing with diverse test patterns, empowering the design of more robust communication systems. The architecture is implemented in chisel and verified on an Intel Agilex 7 FPGA. With the parallel output width set to 256, the design can achieve a throughput of 231.68 Gb/s with a worst case Fmax of 905 MHz.

关键词： Generators Polynomials Registers Clocks Testing field programmable gate arrays Runtime Timing Logic gates Pipeline processing Bit error rate (BER) field-programmable gate arrays (FPGAs) parallel architectures pipeline processing pseudorandom binary sequence (PRBS) reconfigurable architectures serial communication

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Inverse Proportional Chaotification Model for Image Encryption in IoT Scenarios

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第1期72卷 254-264页

作者： Liu, Wenhao Sun, Kehui Wang, Huihai Li, Binglun Chen, Yongjiu Cent South Univ Sch Phys Changsha 410083 Peoples R China Cent South Univ Sch Elect Informat Changsha 410083 Peoples R China Inst Guizhou Aerosp Measuring & Testing Technol Guiyang 550009 Peoples R China

In Internet of Things (IoT) scenarios, the limited computing resources and energy constraints of devices, alongside the growing demand for real-time applications, make secure image transmission challenging. To address this issue, we propose a lightweight image encryption scheme based on chaotic map. Firstly, a new 3-D inverse proportional chaotic map (3D-IPCM) is designed with good robustness. Dynamics confirms that it possesses key characteristics, including a broad and continuous chaotic range, all positive Lyapunov exponents (LEs), high permutation entropy (PE) complexity and even distribution. Then, a new pseudorandom number generator (PRNG) is designed based on this map, which successfully passes all NIST and TestU01 tests, even with 16-bit calculation precision. Next, this PRNG is employed for image encryption in IoT scenarios. In the cryptosystem, a chromosome crossover (CC)-based scrambling algorithm is proposed, along with a diffusion algorithm that achieves strong resistance to differential attack in just two rounds of row diffusion. Simulation and analysis verify that the cryptosystem has strong resistance to common attacks and low cost. For 256x256 images, its average number of pixels change rate (NPCR) and unified average changing intensity (UACI) are 100% and 33.40%, respectively, and the encryption time is only 7.4 ms. Ultimately, we implement the algorithm on FPGA, thus confirming its capacity for parallel acceleration.

关键词： Encryption Internet of Things Security Costs Chaotic communication field programmable gate arrays Sun Resistance Degradation Complexity theory Chaos chaotic system pseudorandom number generator (PRNG) image encryption field-programmable gate array (FPGA) Internet of Things (IoT)

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Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS

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IEEE ACCESS 2025年 13卷 6594-6605页

作者： Rubino, Roberto Musolino, Francesco Toledo, Pedro Chen, Yong Richelli, Anna Crovetti, Paolo S. Analog Devices Inc I-70021 Milan Italy Politecn Torino DET I-10129 Turin Italy Synopsys P-2740267 Lisbon Portugal Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Univ Brescia Dept Informat Engn I-25123 Brescia Italy

The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030 mu m(2) and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18dB-SFDR, a 65.59dB-THD and a 56.09dB SINAD, resulting in 9.02ENOB, with a power dissipation of just 3.3 mu W, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (FOMA) of 166dB (175dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800 mu m(2) and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81dB-SFDR, a 77.52dB-THD and a 65.82dB-SINAD (10.64ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOMA) of 172dB (178dB).

关键词： Clocks Calibration Capacitance System-on-chip Resistance Prototypes Impedance field programmable gate arrays Discharges (electric) Codes D/A converter (DAC) relaxation D/A converter (ReDAC) ultra-low area digital-based ultra-low power ultra-low voltage Internet of Things (IoT) biosensors

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An Efficient and Reconfigurable Post-Quantum Crypto-Processor for SPHINCS

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2252-2262页

作者： Huang, Tianze Lu, Jiahao Liu, Dongsheng Luo, Zhixiang Cheng, Chi Li, Aobo Chen, Lei Yang, Shuo Zhang, Jiaming Li, Xiang Huazhong Univ Sci & Technol Sch Integrated Circuits Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan 430074 Peoples R China China Univ Geosci Sch Comp Sci Wuhan 430074 Peoples R China

SPHINCS+ is the sole hash-based digital signature scheme among the selected post-quantum cryptography (PQC) in 2022. This algorithm possesses the ability to resist attacks from both classical and quantum computers. Due to the extensive computations and different data widths for various parameters, its hardware implementation faces the weakness of long operation time, large area requirement, and low flexibility. This paper presents an efficient and reconfigurable SPHINCS+ processor. The proposed on-the-fly WOTS+ public key generation scheme with unified chain address generator accelerated the most time-consuming operations. This optimization achieves efficient resource utilization. A security switch mechanism resolves the bit misalignment among different data widths with resource reduction. Finally, we introduce a grouped subtree and segmented signature streaming scheme. They reduce the memory to 16k bytes. The processor consumes 29410 LUTs, 14090 FFs, 4 BRAMs on Artix-7 FPGA and achieves 1.04x/2.41x ATPs (area-time-product) optimizations in Sign/ Verify with the advantage of supporting all security levels of SPHINCS+.

关键词： Vegetation Hardware Hash functions Quantum computing Generators Digital signatures Computers NIST field programmable gate arrays Authentication Post-quantum cryptography SPHINCS plus hash-based signature hardware efficiency reconfigurable processor

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