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Design of Synchronous Multichannel Cascadable High-Speed Arbitrary Waveform Generator

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Zhao, Wenhao Wang, Houjun Liu, Ke Xiao, Yindong Univ Elect Sci & Technol China Shenzhen Inst Adv Study Shenzhen 518110 Guangdong Peoples R China Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Sichuan Peoples R China

The output bandwidth and the capacity to generate multiple analog outputs with high-accuracy synchronization are essential specifications of an arbitrary waveform generator (AWG). The popularity of high-speed digital-to-analog converter (DAC) and high data throughput double data rate synchronous dynamic random access memory (DDR SDRAM) has led to current AWG reaching the output wideband with gigahertz level. However, as the operating frequency increases, the signal propagation delay in the AWG becomes more sensitive to the clock signals, the trigger signal, and the channel differences, making the AWG's output synchronization more challenging. For the accuracy synchronization of high-speed wideband AWG outputs, this article establishes a propagation model by analyzing the effects of clock signals, the trigger signal, and the channel differences on the propagation delay of waveform signals in the AWG channel. The corresponding synchronization design methods are discussed for each factor, and a synchronization structure of scalable multichannel high-speed AWG is proposed. Furthermore, a channel delay adjustment technique based on the digital method is used to correct the time skew between outputs. Finally, an experimental platform for eight-channel AWG and two-channel AWG has been designed according to the proposed method. The experimental results show that the number of output channels of AWG can be adjusted quickly according to the proposed scalable structure, and the synchronization accuracy can reach +/- 5 ps at 5-GS/s sampling rate.

关键词： Clocks Synchronization field programmable gate arrays Training Data mining Artificial intelligence Propagation delay SDRAM Control systems Circuits Accuracy synchronization multichannel high-speed arbitrary waveform generator (AWG) propagation model scalable synchronization structure time skew correction based on digital method

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Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages

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IEEE TRANSACTIONS ON COMPUTERS 2025年第4期74卷 1306-1321页

作者： Wei, Kaijie Amano, Hideharu Niwase, Ryohei Yamaguchi, Yoshiki Miyoshi, Takefumi Keio Univ Ctr Sustainable Quantum AI Tokyo 1080073 Japan Univ Tokyo Syst Design Lab Bunkyo Ku Tokyo 1130032 Japan Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki 3058573 Japan WasaLabo LLC Tokyo 1940045 Japan

Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with n qubits requires 2(n+4) bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.

关键词： Qubit Quantum computing Quantum circuit Integrated circuit modeling Computational modeling field programmable gate arrays Logic gates Supercomputers Memory management Graphics processing units State vector quantum circuit simulation quantum computer FPGA Qulacs HLS Serial ATA

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A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第1期44卷 39-51页

作者： Xu, Junge Zhang, Fan Jin, Wenguang Yang, Kun Wang, Zeke Jiang, Weixiong Ha, Yajun Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China Zhejiang Univ Coll Comp Sci & Technol Hangzhou 310027 Peoples R China Zhengzhou Xinda Inst Adv Technol Zhengzhou 450001 Peoples R China ShanghaiTech Univ Sch Informat Sci & Technol Shanghai 201210 Peoples R China

With increasing computation of various applications, dynamic voltage and frequency scaling (DVFS) is gradually deployed on FPGAs to improve performance and save energy. However, its reliability and security have not been sufficiently evaluated, which incurs quite many concerns. In this article, we propose an evaluation framework for deep investigation of stealthy DVFS fault injection attacks on the state-of-the-art deep neural networks (DNNs) deployed on modern FPGAs. The evaluation framework mainly consists of a DVFS attack striker and a time-to-digital converter (TDC)-based hardware profiler. Two modes of evaluation are derived, and their effectiveness is demonstrated on a platform composed of a SkyNet accelerator and three ImageNet models built on a Xilinx deep learning processor unit (DPU). Experimental results show that more than 99% detection accuracy loss can be measured targeting at all tested DNN models under prospective operation mode but without any performance degradation in frame per second (FPS). In our investigation of sensitive layer mode, more than 93% average accuracy loss with 84.7% fault probability can be measured on a single bundle of the SkyNet. We characterize the vulnerabilities of different DNN layers subject to DVFS attacks through leveraging the TDC-based hardware profiler to precisely control the timing of fault injection.

关键词： Circuit faults field programmable gate arrays Artificial neural networks Voltage control Hardware acceleration Deep learning Energy efficiency Deep learning accelerator dynamic voltage and frequency scaling (DVFS) fault injection attack image recognition time-to-digital converter (TDC)

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Remote Power Side- Channel Attacks on FPGAs

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2025年第1期42卷 13-19页

作者： Zhao, Mark Suh, G. Edward Stanford Univ Dept Elect Engn Stanford CA 94305 USA Nvidia Westford MA 01886 USA Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA

Editor's notes: Side-channel attacks, like those exploiting power and timing, are generally thought to require physical access to a system. This research challenges that idea by demonstrating how such attacks can be carried out on remote systems without physical access. It emphasizes the need to rethink how modern shared-FPGA systems are designed, prioritizing security as a core consideration. -Jeyavijayan Rajendran, Texas AM University, USA

关键词： field programmable gate arrays Logic Circuits Monitoring Power demand Logic gates Switches Channel models Side-channel attacks field programmable gate array ring oscillator power analysis attack side-channel attack system-on-chip

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A Hybrid Scrubber Based on the SEM and the PicoBlaze for Artix-7 FPGAs in the COMET Read-Out Electronics

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 240-248页

作者： Hamada, Eitaro Igarashi, Youichi Ueno, Kazuki High Energy Accelerator Res Org KEK Inst Particle & Nucl Studies Tsukuba 3050801 Japan Osaka Univ Dept Phys Osaka 5650871 Japan

When operating field-programmable gate arrays (FPGAs) in a radiation environment, single-event upsets (SEUs) induced in the configuration memory can alter the functionality of the firmware. This alteration can disrupt the correct operation of an FPGA. Even with a typical SEU mitigation design incorporated into the FPGA, unrecoverable errors can still occur, which can only be corrected by re-downloading FPGA firmware. In this study, we developed a Hybrid Scrubber Design that can correct multibit upsets (MBUs), which are one of the main causes of unrecoverable errors. The Hybrid Scrubber Design consists of the Advanced Micro Devices (AMD) soft error mitigation (SEM) and the AMD microprocessor (PicoBlaze). When a single-bit upset (SBU) occurs, the SEM in the FPGA corrects it in a short time. The FPGA communicates with an external computer only when an MBU occurs and then the PicoBlaze corrects it. We incorporated the Hybrid Scrubber Design into the FPGA on the readout electronics for the COherent Muon to Electron Transition (COMET) experiment. We conducted neutron irradiation tests and measured the unrecoverable error rate, which was calculated by dividing the observed number of unrecoverable errors by the neutron fluence. Compared to incorporating the SEM, which is a typical SEU mitigation design, the Hybrid Scrubber Design reduced the unrecoverable error rate by 80%.

关键词： field programmable gate arrays Materials handling Error correction codes Prevention and mitigation Comets Microprogramming Neutrons Maintenance engineering Detectors Single event upsets field-programmable gate array (FPGA) hybrid muon neutron single-event upset (SEU) the COherent Muon to Electron Transition (COMET)

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A Low-Complexity and High-Throughput Hardware Design for Lempel-Ziv 4 Compression Algorithm

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Chen, Tao Song, Suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

The Lempel-Ziv (LZ) 4 compression algorithm, widely used in data transmission and storage, faces the challenge of high-speed implementation and increased complexity in the era of big data. Therefore, this paper proposes a single-core parallel architecture for LZ4 algorithm with high throughput and low complexity. Firstly, to enhance throughput, two innovative approaches are introduced from the perspective of parallelism and frequency with an acceptable compression ratio loss: each parallelization window is restricted to performing a single match, bridging the gap between actual and theoretical parallelism;the feedback loop in the circuit is broken by utilizing the spatial correlation between adjacent matches for higher frequency. Secondly, two optimization schemes are employed on resource-consuming modules to achieve low complexity. Multi-port hash tables using Live Value Table (LVT) are improved based on inherent data characteristics, significantly reducing the hardware resource consumption while ensuring excellent scalability on hash table depth and frequency. The match comparison operation is moved ahead, further reducing the logic resources by 64.36%. Finally, our design is implemented on FPGA and ASIC platforms. Experimental results on FPGA demonstrate that the proposed architecture achieves a throughput of 17.39 Gb/s, exhibiting a 2.86x improvement over the state-of-the-art, along with a 6.46x enhancement in area efficiency. Further optimizations including Canonic Signed Digit (CSD) coding and computational reuse on the ASIC platform result in a 45x improvement in area efficiency.

关键词： Hardware Throughput Parallel processing Complexity theory field programmable gate arrays Compression algorithms Encoding Signal processing algorithms Parallel architectures Logic Lossless data compression LZ4 algorithm FPGA ASIC high throughput low complexity hardware accelerator

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Evaluation of SmartNIC Devices for Use in Trigger and Data Acquisition Systems

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 355-363页

作者： Berg, Andreas Klavenes Abud, Adam Abed Gamberini, Enrico Poulsen, Anders Hjelm Khartchenko, Evgueny Miotto, Giovanna Lehmann Mckenzie, Graham Sipos, Roland Zheng, Jeff CERN CH-1211 Geneva Switzerland Norwegian Univ Sci & Technol Dept Comp Sci N-7034 Trondheim Norway Arm Norway N-7011 Trondheim Norway Silicom Denmark DK-2860 Soborg Denmark Intel Corp UK Ltd Swindon SN3 1RJ England Intel Co Altera Leicester LE9 9FG England Silicom Ltd IL-4464323 Kefar Sava Israel

This article presents an evaluation of SmartNIC devices in the context of Trigger and Data AcQuisition (TDAQ) systems. SmartNIC devices represent an emerging technology whose aim is to offload network tasks and infrastructure control plane software from the CPU. Such devices are particularly relevant for TDAQ systems where high rates in the orders of TB/s are produced in large detectors such as the deep underground neutrino experiment (DUNE). In this context, the potential use case of SmartNICs is to perform a quasi-real-time reduction of the incoming data streams by identifying only the interesting signals. The goal is to sustain a number of similar to 10 Gb data streams aggregated on 100 Gb interfaces and transmit the results to the host machine. An application was developed to provide a testing environment, measuring the achieved throughput in two cases. In the first case, only the total throughput is considered, and the workload is evenly distributed across the available hardware. In the second case, a constraint of processing a number of discrete data streams is added. The application was shown to handle up to similar to 130 Gbps of incoming data when distributing the workload evenly on the available hardware resources of 8 CPU cores. In this contribution, we show the testing results, optimizations, and hardware tuning of the technology when performing a workload suitable for TDAQ applications.

关键词： Detectors Streams Servers Hardware Throughput Software Protocols field programmable gate arrays Ethernet Data acquisition dataplane development kit (DPDK) HPC SmartNIC

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HAST: A Hardware-Efficient Spatio-Temporal Correlation Near-Sensor Noise Filter for Dynamic Vision Sensors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第3期72卷 1332-1345页

作者： Gopalakrishnan, Pradeep Kumar Chang, Chip-Hong Basu, Arindam CNRS CREATE Ltd Singapore 138602 Singapore Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore City Univ Hong Kong Dept Elect Engn Hong Kong Peoples R China

The Dynamic Vision Sensor (DVS) is a bio-inspired image sensor which has many advantages such as high dynamic range, high bandwidth, high temporal resolution and low power consumption for Internet of Video Things and Edge Computing applications. However, spuriously generated Background Activity (BA) noise events can significantly degrade the quality of DVS output and cause unnecessary computations throughout the image processing chain, reducing its energy efficiency. Near-sensor filters can mitigate this problem by preventing the BA noise events from reaching downstream stages. In this paper, we propose a novel, hardware-efficient, spatio-temporal correlation filter (HAST) for near-sensor BA noise filtering. It uses compact two-dimensional binary arrays along with simple, arithmetic-free hash-based functions for storage and retrieval operations. This approach eliminates the need to use timestamps for determining the chronological order of events. HAST uses much lower memory and energy compared to other hardware-friendly filters (BAF/STCF) while matching their performance in simulations with standard datasets;for a sensor of resolution 346 x 260 pixels, it requires only 5-18% of their memory, and about 15% of their energy per event for correlation time tau ranging from 1 to 50 ms. The memory and energy gains of the filter increase with sensor resolution. In FPGA implementation, HAST achieves about 29% higher throughput than BAF/STCF while utilizing only about 5% of their memory. The filter parameter values can be chosen by Design Space Exploration (DSE) for optimized performance-resource trade-offs based on application requirements.

关键词： Noise Voltage control Memory management Filtering algorithms Correlation Information filters Vision sensors Robot sensing systems Energy resolution field programmable gate arrays Dynamic vision sensor neuromorphic vision sensor background activity noise spatio-temporal correlation filtering hash function field programmable gate arrays

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Parallel implementation by the FPGA of phase diversity based on an improved particle swarm optimization algorithm

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APPLIED OPTICS 2025年第1期64卷 30-39页

作者： Kou, Xianzheng Li, Dequan Wang, Dong Zhang, Bin Chinese Acad Sci Changchun Inst Opt Fine Mech & Phys Changchun 130033 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China

The phase diversity (PD) algorithm based on population optimization has been widely used in wavefront sensing due to advantages such as a simple optical path, no customized sensors, and low cost. However, this method requires a large amount of computation, and the optimization process is seriously disturbed by local extreme values, with the calculation time increasing with the size of the population. Therefore, it is unsuitable for scenarios with limited computing power and energy consumption, such as space optical systems. The field programmable gate array (FPGA) is a device widely used in the aerospace field with high flexibility, reconfigurability, high reliability, and low power consumption. Based on the characteristics of FPGA parallel computing, this paper analyzes and improves the phase diversity algorithm and the particle swarm optimization (PSO) used for its solution, making it suitable for a parallel algorithm architecture, and finally realizing FPGA board-level verification. The results show that this work can improve the computational speed and performance of the phase diversity algorithm based on population optimization. (c) 2024 Optica Publishing Group. All rights, including for text and data mining (TDM), Artificial Intelligence (AI) training, and similar technologies, are reserved.

关键词： Adaptive optics field programmable gate arrays Fourier transforms Optical systems Phase diversity Wave front sensing

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Longest-First Search Using Bloom Filter: Algorithm and FPGA Implementation

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IEEE ACCESS 2025年 13卷 49354-49361页

作者： Lee, Jinsol Lim, Hyesook Ewha Womans Univ Dept Elect & Elect Engn Seoul 03760 South Korea

Due to the surge in Internet traffic and the rapid increase in forwarding table entries, achieving wire-speed packet forwarding in Internet routers demands both algorithmic enhancements and hardware innovations. In this paper, we propose the longest-first search algorithm with a Bloom filter that stores prefixes in a leaf-pushing trie. Our approach utilizes an on-chip Bloom filter to indicate the presence of prefixes within the trie, while an off-chip hash table stores the corresponding output port information for each prefix. For each incoming IP address, the Bloom filter query begins from the longest length, reducing the queried number of bits by one for each negative result. The off-chip hash table is only accessed when the query to the Bloom filter produces a positive result. Therefore, access to the slower off-chip memory is minimized to once, given a reasonable Bloom filter size. The proposed approach is simulated using C++ and constructed with Verilog for field programmable gate array (FPGA) implementation. The experimental results indicate that the proposed approach achieves the throughput of 0.8 million packets per second at a clock frequency of 100MHz.

关键词： Filtering algorithms IP networks Information filters Filtering theory field programmable gate arrays Matched filters Lenses Internet System-on-chip Hash functions Binary trie Bloom filter FPGA IP address lookup leaf-pushing Verilog HDL

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