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Implementation of Continuous Control Set Model Predictive Control Method for PMSM on FPGA

IEEE ACCESS 2023年 11卷 12414-12425页

作者： Wang, Bozhi Jiao, Jiye Xue, Ziyang Xian Univ Posts & Telecommun Coll Elect Engn Xian 710121 Peoples R China Xian Univ Posts & Telecommun Coll Comp Sci Xian 710121 Peoples R China

The generalized predictive control (GPC-MPC) algorithm adopts an optimal control strategy, which requires online matrix inversion operation and is difficult to be applied to real-time control systems. Therefore, the permanent magnet synchronous motor (PMSM) drive experiments, using the GPC-MPC algorithm with constraints, are primarily performed in a simulation environment. This paper proposes a new matrix inversion and its circuit design method to complete the above experiments in an embedded environment. By using the calculation steps of matrix block decomposition and reinversion, the parallelism of matrix calculation and the regularity of storage address are improved, and the speed of matrix inversion is accelerated. Also, the model-based design (MBD) method is used to complete the design and verification of the rest of the algorithm, which speeds up the implementation and deployment of the algorithm. Finally, the GPC-MPC algorithm control experiments with current constraints are implemented on the field programmable gate array (FPGA) experimental board. The experimental results show that the proposed design method has a good control effect and computational efficiency.

关键词： Prediction algorithms field programmable gate arrays Matrix decomposition Symmetric matrices Optimization Mathematical models Heuristic algorithms Matrix inverse generalized predictive control (GPC-MPC) permanent magnet synchronous motor (PMSM) model-based design (MBD) field programmable gate array (FPGA)

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A Resource Efficient Software-Hardware Co-Design of Lattice-Based Homomorphic Encryption Scheme on the FPGA

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IEEE TRANSACTIONS ON COMPUTERS 2023年第5期72卷 1247-1260页

作者： Paul, Bikram Yadav, Tarun Kumar Singh, Balbir Krishnaswamy, Srinivasan Trivedi, Gaurav Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati 781039 Assam India

Lattice-based homomorphic encryption schemes provide strong resistance against quantum and classical computer-based adversary security attacks. In this article, we present a software-hardware co-design of two partially homomorphic encryption (PHE) schemes employing an ARM-System on Chip (ARM-SoC) and an field programmable gate array (FPGA). This provides necessary acceleration to PHE methods in the ecosystem mentioned above. The first PHE scheme is designed for generic homomorphic encryption, while the second scheme is aimed at resource optimized lightweight IoT-driven applications. For seamless assimilation, a robust and reliable low latency data transfer protocol is developed between the FPGA-based accelerator IP and ARM-SoC host system. The proposed PHE schemes are realized using Verilog hardware description language on multiple FPGA platforms. The proposed lightweight scheme is 52.71x more resource-efficient than the pipelined BGV RLWE-based method. It exhibits 1.43x and 1.29x better throughput than non-pipelined and pipelined realizations of the BGV RLWE-based scheme. The proposed hardware accelerators realized on FPGA platforms having lesser clock speed and consuming lower resources showcase significant speedup compared to their software implementations making our proposed method an efficient alternative to enhance security in edge-enabled IoT devices.

关键词： Homomorphic encryption field programmable gate arrays Internet of Things Hardware acceleration Computer architecture Lattices IP networks Partially homomorphic encryption hidden subspace membership problem learning with errors FPGA system-on-chip low power device

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An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第12期70卷 4816-4825页

作者： Shukla, Satyam Utkarsh, Md Azam, Md Ray, Kailash Chandra Indian Inst Technol Patna Dept Elect Engn Patna 801106 Bihar India

In the modern era, FPGA-based soft-core processors have gained much attention in space applications due to their flexibility and ease of integration. In such applications, radiation can produce a Single Event Upset (SEU) in CMOS devices that may lead to severe errors in microprocessors. The instruction decoder is one of the most critical components of a microprocessor. Any error in the instruction decoder due to SEU may destroy the flow of the program, and it may lead to complete system failure. Hence, a novel parity-based fault-tolerant instruction decoder architecture is proposed for dual-core processors implemented on FPGAs. In case of occurrence of SEU, the instruction decoders of two cores are swapped for fault-masking against single-bit error. Looking at the increased adaptability of RISC-V ISA, the proposed fault-tolerant instruction decoder is integrated with an in-house designed RV32IM processor using Verilog HDL. Further, the proposed fault-tolerant processor architecture is prototyped on commercially available NEXYS4 DDR FPGA board by employing the soft error mitigation (SEM) IP core of Xilinx Inc. to inject SEU in real time to study the fault tolerance capability. The proposed design is compared with the state-of-the-art SEU mitigation approaches. The main advantage of the proposed architecture is that the LUT (Look up table) overhead is 167.06% less, and power overhead is 46.87% less compared to the conventional triple modular redundancy (TMR) approach to mitigate SEU. The proposed design is able to provide 71.2% fault tolerance compared to the unprotected design.

关键词： Decoding Fault tolerant systems Program processors Registers field programmable gate arrays Circuit faults Redundancy Instruction decoder fault-tolerant design RISC-V processor architectural design FPGA prototype

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Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2023年第1期13卷 108-118页

作者： Shin, Duckgyu Onizawa, Naoya Gross, Warren J. Hanyu, Takahiro Tohoku Univ Grad Sch Engn Sendai Miyagi 9808577 Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi 9808577 Japan McGill Univ Dept Elect & Comp Engn Montreal PQ H3A 0G4 Canada

Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows. Recently, a stochastic simulated annealing (SSA) algorithm that converges faster than conventional SA has been reported. In this paper, we present a hardware-aware SSA (HA-SSA) algorithm for memory-efficient FPGA implementations. HA-SSA can reduce the memory usage of storing intermediate results while maintaining the computing speed of SSA. For evaluation purposes, the proposed algorithm is compared with the conventional SSA and SA approaches on maximum cut combinatorial optimization problems. HA-SSA achieves a convergence speed that is up to 114-times faster than that of the conventional SA algorithm depending on the maximum cut problem selected from the G-set which is a dataset of the maximum cut problems. HA-SSA is implemented on a field-programmable gate array (FPGA) (Xilinx Kintex-7), and it achieves up to 6-times the memory efficiency of conventional SSA while maintaining high solution quality for optimization problems.

关键词： Hardware Stochastic processes Optimization Simulated annealing field programmable gate arrays Computational modeling Probabilistic logic Stochastic computing simulated annealing FPGA combinatorial optimization problem

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FPGA Bitstream Modification: Attacks and Countermeasures

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IEEE ACCESS 2023年 11卷 127931-127955页

作者： Moraitis, Michail KTH Royal Inst Technol S-16440 Stockholm Sweden

Advances in field-programmable gate Array (FPGA) technology in recent years have resulted in an expansion of its usage in a very wide spectrum of applications. Apart from serving the traditional prototyping purposes, FPGAs are currently regarded as an integral part of embedded systems used in many industries, including communication, medical, aerospace, automotive, and military. Moreover, the emerging trend of AI has found FPGAs to be at the technological forefront with their use as deep learning acceleration platforms. The demand for FPGAs has grown to the point that major companies (e.g. Amazon) are offering cloud-based access to FPGAs, known as FPGA-as-a-Service. In many applications, FPGAs handle sensitive data and/or host cryptographic algorithm implementations. These FPGAs are not always located in a tamper-resistant environment, which makes their security a major concern, especially in light of the ever-growing number of publications demonstrating effective attacks specifically tailored to exploit the physical traits of FPGA implementations. In this survey, we cover the subset of those attacks that involve tampering with the FPGA configuration bitstream. We start by discussing how the FPGA vendors attempt to protect their products and how malicious parties try to overcome this protection. We then proceed to present the different bitstream modification attacks that can be found in the literature organized according to their targets. Finally, we present various countermeasures that can be deployed, drawing on bibliographic references from works specifically focused on FPGA bitstream protection, as well as those initially proposed for different purposes or devices that can be adapted for bitstream protection.

关键词： field programmable gate arrays Surveys Cryptography Random access memory Routing Performance evaluation Microcontrollers Physical security reverse engineering cryptographic implementation FPGA bitstream encryption bitstream modification

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A Delay-Free Decoupling Method for FPGA-Based Real-Time Simulation of Power Electronic Systems

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL E...

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL ELECTRONICS 2025年第1期6卷 391-402页

作者： Yang, Yiming Xu, Jin Wang, Keyou Wu, Pan Li, Zirun Li, Guojie Shanghai Jiao Tong Univ Key Lab Control Power Transmiss & Convers Minist Educ Shanghai 200240 Peoples R China North China Branch State Grid Beijing 100053 Peoples R China

The decoupling method based on the natural or inserted artificial delays, when applied to the simulation of power electronic (PE) systems, may encounter challenges such as inadequate length of delay lines or numerical instability and precision issues due to the high-frequency voltage/current variations at interfaces. To deal with the challenge, a delay-free decoupling method is proposed in this article. The method reduces both the dimension of matrix multiplication and the number of switch state combinations without sacrificing numerical stability and compresses the calculation progress by representing the decoupled system with the discrete state-space equation. The PE system is decoupled at the series/parallel interface of submodules, treating currents as boundary variables linked to each submodule's extended port. A preliminary formula for these variables is derived by simultaneously solving nodal voltage equations and kirchhoff voltage laws (KVL) equations. Submodule solutions are compacted and parallelized based on the discrete state-space equations. These equations are then substituted back and decomposing boundary variables into independent segments, to achieve parallelization of boundary variable solutions. The proposed method is validated through real-time simulation of cascaded PE systems on an field programmable gate array (FPGA) platform with a 250 ns time step. Results show that it achieves high precision compared to nondecoupled systems in power systems computer aided design (PSCAD) across diverse transient conditions. Additionally, it boosts the simulation scale by roughly 2-7 times on the FPGA-based platform compared to nondecoupled nodal analysis.

关键词： Real-time systems Mathematical models Sparse matrices field programmable gate arrays Switches Delays Accuracy Voltage Switching circuits Parallel processing Delay-free decoupling EMT field programmable gate array (FPGA) modular multilevel converter (MMC) power electronic transformer (PET) real-time simulation

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Fast SDDRE-Based Maneuvering-Target Interception at Prespecified Orientation

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IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY 2023年第6期31卷 2895-2902页

作者： Lin, Li-Gang Wu, Ruei-Syuan Huang, Ping-Kong Xin, Ming Wu, Chin-Tien Lin, Wen-Wei Natl Cent Univ Dept Mech Engn Taoyuan 32001 Taiwan Natl Yang Ming Chiao Tung Univ Dept Appl Math Hsinchu Taiwan Univ Missouri Dept Mech & Aerosp Engn Columbia MO 65211 USA

This study considers the 3-D guidance law based on target lead angle information and the state-dependent differential Riccati equation (SDDRE) scheme. In an application-oriented manner, it presents theories to significantly improve critical computational performance and thus aims at a fast implementation for impact-angle-constrained interception of agile maneuvering targets. More specifically, regarding the two major computational burdens using SDDRE, we have replaced the burden in numerical applicability checking by a simple, equivalent, and closed-form condition for the entire state space, which is actually the dominant burden as supported by complexity analysis and extensive validations. Notably, the proposed analysis not only complements the early findings of applicability guarantee in literature, but also promotes the efficiency of the proposed philosophy when compared to the classic method, where the latter has caused concerns/reservations due to its feasibility and difficulty. On the other hand, we have largely mitigated the second major burden of SDDRE by-after exhaustive trials-selecting the most efficient Riccati-equation solver until the latest benchmarks. Such evaluations are: 1) in favor of a much-less-known achievement, rather than the common QR-based benchmark and 2) subject to both numerical and hardware experiments including, notably, implementations on microcontrollers and field-programmable gate arrays.

关键词： Lead Hardware Riccati equations field programmable gate arrays Computational efficiency Aerospace electronics Nonlinear dynamical systems impact angle constraint maneuvering-target interception spatial lead angle guidance state-dependent differential Riccati equation (SDDRE)

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A Visionary Look at the Security of Reconfigurable Cloud Computing

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PROCEEDINGS OF THE IEEE 2023年第12期111卷 1548-1571页

作者： Stojilovic, Mirjana Rasmussen, Kasper Regazzoni, Francesco Tahoori, Mehdi B. Tessier, Russell Ecole Polytech Fed Lausanne EPFL Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Univ Oxford Dept Comp Sci Oxford OX1 3QD Oxon England Univ Amsterdam NL-1098 XH Amsterdam Netherlands Karlsruhe Inst Technol D-76131 Karlsruhe Germany Univ Massachusetts Amherst Dept Elect & Comp Engn Amherst MA 01003 USA

field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking and signal processing, among many others. Unfortunately, fine-grained programmability also makes FPGAs a security risk. Here, we review the current scope of attacks on cloud FPGAs and their remediation. Many of the FPGA security limitations are enabled by the shared power distribution network in FPGA devices. The simultaneous sharing of FPGAs is a particular concern. Other attacks on the memory, host microprocessor, and input/output channels are also possible. After examining current attacks, we describe trends in cloud architecture and how they are likely to impact possible future attacks. FPGA integration into cloud hypervisors and system software will provide extensive computing opportunities but invite new avenues of attack. We identify a series of system, software, and FPGA architectural changes that will facilitate improved security for cloud FPGAs and the overall systems in which they are located.

关键词： field programmable gate arrays Cloud computing Servers Security Data centers Central Processing Unit Switches denial-of-service (DoS) attack fault injection field-programmable gate array (FPGA) secure computing side-channel attack

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Comparison and Selection of Spike Encoding Algorithms for SNN on FPGA

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2023年第1期17卷 129-141页

作者： Wang, Kuanchuan Hao, Xinyu Wang, Jiang Deng, Bin Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China

The information in Spiking Neural Networks (SNNs) is carried by discrete spikes. Therefore, the conversion between the spiking signals and real-value signals has an important impact on the encoding efficiency and performance of SNNs, which is usually completed by spike encoding algorithms. In order to select suitable spike encoding algorithms for different SNNs, this work evaluates four commonly used spike encoding algorithms. The evaluation is based on the FPGA implementation results of the algorithms, including calculation speed, resource consumption, accuracy, and anti-noiseability, so as to better adapt to the neuromorphic implementation of SNN. Two real-world applicaitons are also used to verify the evaluation results. By analyzing and comparing the evaluation results, this work summarizes the characteristics and application range of different algorithms. In general, the sliding window algorithm has relatively low accuracy and is suitable for observing signal trends. Pulsewidth modulated-Based algorithm and step-forward algorithm are suitable for accurate reconstruction of various signals except for square wave signals, while Ben's Spiker algorithm can remedy this. Finally, a scoring method that can be used for spiking coding algorithm selection is proposed, which can help to improve the encoding efficiency of neuromorphic SNNs.

关键词： Encoding field programmable gate arrays Software algorithms Hardware Classification algorithms Approximation algorithms Neuromorphics field programmable gate array (FPGA) spike encoding algorithms spiking neural network

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Addressing the programming challenges of practical interferometric mesh based optical processors

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OPTICS EXPRESS 2023年第15期31卷 23851-23866页

作者： Mojaver, Kaveh (Hassan) Rahbardar Zhao, Bokun Leung, Edward Safaee, S. Mohammad Reza Liboiron-Ladouceur, Odile McGill Univ Elect & Comp Engn Dept Montreal PQ Canada Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada

We demonstrate a novel mesh of Mach-Zehnder interferometers (MZIs) for pro-grammable optical processors. We thoroughly analyze the benefits and drawbacks of previously known meshes and compare our newly proposed mesh with these prior architectures, highlighting its unique features and advantages. The proposed mesh, referred to as Bokun mesh, is an architecture that merges the attributes of the prior topologies Diamond and Clements. Similar to Diamond, Bokun provides diagonal paths passing through every individual MZI enabling direct phase monitoring. However, unlike Diamond and similar to Clements, Bokun maintains a minimum optical depth leading to better scalability. Providing the monitoring option, Bokun's programming is faster improving the total energy efficiency of the processor. The performance of Bokun mesh enabled by an optimal optical depth is also more resilient to the loss and fabrication imperfections compared to architectures with longer depth such as Reck and Diamond. Employing an efficient programming scheme, the proposed architecture improves energy efficiency by 83% maintaining the same computation accuracy for weight matrix changes at 2 kHz.

关键词： field programmable gate arrays Optical components Optical depth Optical neural systems Optical processing devices Phase shift

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