This report describes the design of a modular, massive-parallel, neural-network (NN)-based vector quantizer for real-time video coding. The NN is a self-organizing map (SOM) that works only in the training phase for c...
详细信息
This report describes the design of a modular, massive-parallel, neural-network (NN)-based vector quantizer for real-time video coding. The NN is a self-organizing map (SOM) that works only in the training phase for codebook generation, only at the recall phase for real-time image coding, or in both phases for adaptive applications. The neural net can be learned using batch or adaptive training and is controlled by an inside circuit, finite-state machine-based hard controller. The SOM is described in VHDL and implemented on electrically (FPGA) and mask (standard-cell) programmable devices. (C) 2007 Elsevier B.V. All rights reserved.
A field programmable gate array (FPGA)-based physical layer phase-encryption technique suitable for applications in high-speed passive optical networks is presented. The physical layer ciphering technique is based on ...
详细信息
A field programmable gate array (FPGA)-based physical layer phase-encryption technique suitable for applications in high-speed passive optical networks is presented. The physical layer ciphering technique is based on a combination of multilevel phase shift keying (PSK) modulation and binary differential PSK. A mathematical model of the system is first derived and numerical simulations are obtained using Mathematica. Expressions for the probability of error for both a legitimate and eavesdropping receiver are derived and evaluated numerically. The results from experimental implementation using high-speed phase modulators and FPGAs are also given to further prove the efficacy of the presented technique. The macroscopic cryptography technique offers completely opaque communication over trans-oceanic distances, gigabit date rates and multiple wavelengths.
Elliptic curve cryptography (ECC) and Tate pairing are two new types of public-key cryptographic schemes that become popular in recent years. ECC offers a smaller key size compared to traditional methods without sacri...
详细信息
Elliptic curve cryptography (ECC) and Tate pairing are two new types of public-key cryptographic schemes that become popular in recent years. ECC offers a smaller key size compared to traditional methods without sacrificing Security level. Tate pairing is a bilinear map commonly used in identity-based cryptographic schemes. Therefore, it is more attractive to implement these schemes by using hardware than by using software because of its computational expensiveness. In this paper, we propose field programmable gate array (FPGA) implementations of the elliptic curve point Multiplication in Galois field GF(2(283)) and Tate pairing computation in GF(2(283)). Experimental results demonstrate that, compared with previously proposed approaches, Our FPGA implementations of ECC and Tate pairing can speed up by 31.6 times and 152 times, respectively. (c) 2008 Elsevier B.V. All rights reserved.
In wireless sensor networks (WSN) for time-critical applications a fast transmission of sensor data is required for proper system operation. This paper presents an ultra-fast ultra-wideband (UWB) transceiver for sub-m...
详细信息
In wireless sensor networks (WSN) for time-critical applications a fast transmission of sensor data is required for proper system operation. This paper presents an ultra-fast ultra-wideband (UWB) transceiver for sub-microsecond communication in time-critical WSN. Sensor data is encoded in packets of one byte plus start and stop bits and transmitted with a data rate of 100 Mbit/s. With high-speed analog to digital conversion and digital signal processing less than 200 ns are required for data transmission and reception with possible data transmission every 120 ns. Circuit design and operating principle of the transceiver are explained and measurement results provided to prove its functionality.
Parallel parking is a challenging maneuver for many drivers, especially in crowded cities with heavy traffic congestion and limited parking spaces. This research focuses on the development of an intelligent parallel p...
详细信息
Parallel parking is a challenging maneuver for many drivers, especially in crowded cities with heavy traffic congestion and limited parking spaces. This research focuses on the development of an intelligent parallel parking system. Conventional vehicular control techniques generally require the use of analytical models. However, complexities due to nonlinear car dynamics create multiple challenges when modeling car motion. As fuzzy logic control is appropriate for nonlinear and complex systems where human expert knowledge is available, it is well-suited for the parking application. This paper presents the design and implementation of a real-time fuzzy logic based parallel parking system. Two control units consisting of a main controller and a secondary fuzzy logic controller are utilized. The latter controller is employed for the realization of the wall following task, which has an important role in the parking system. Based on performance and flexibility considerations, the control units are implemented onto a reconfigurable hardware platform, namely a field programmable gate array (FPGA). A prototype vehicle is developed to ensure the proposed algorithm provides vehicular systems with the parallel parking ability.
For practical applications, the fractional order integral and differential operators require to be approximated as stable, causal, minimum-phase integer order systems, which usually leads, in both continuous and discr...
详细信息
ISBN:
(纸本)9780791848067
For practical applications, the fractional order integral and differential operators require to be approximated as stable, causal, minimum-phase integer order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that an approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, field programmable gate arrays (FPGAs), Switched Capacitors Circuits (SCCs), and fieldprogrammable Analog arrays (FPAAs) are used in this paper for the implementation of a fractional order integrator, previously approximated by the recursive Oustaloup's method. The fundamentals of the devices, as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.
This paper introduces a digital implementation of a new simple programmable autowave generator network on a field programmable gate array (FPGA). The network is a two dimensional reaction-diffusion Cellular Neural Net...
详细信息
ISBN:
(纸本)9781424420896
This paper introduces a digital implementation of a new simple programmable autowave generator network on a field programmable gate array (FPGA). The network is a two dimensional reaction-diffusion Cellular Neural Network which consists of relaxation oscillators. The introduced implementation successfully simulates 25,600 neurons in real-time with novel Cellular Neural Processing Network architecture which uses floating-point number format. The implementation allows simulating the network with high numeric resolution and real-time monitoring of the evolution of autowaves. This FPGA implementation of the network provides a suitable platform to explore spatiotemporal behavior and to implement wave computing algorithms.
We describe the fabrication of sub-100-nanometer-sized channels in a fused silica lab-on-a-chip device and experiments that demonstrate detection of single fluorescently labeled proteins in buffer solution within the ...
详细信息
ISBN:
(纸本)9780819472557
We describe the fabrication of sub-100-nanometer-sized channels in a fused silica lab-on-a-chip device and experiments that demonstrate detection of single fluorescently labeled proteins in buffer solution within the device with high signal and low background. The fluorescent biomolecules are transported along the length of the nanochannels by clectrophoresis and/or electro-osmosis until they pass into a two-focus laser irradiation zone. Pulse-interleaved excitation and time-resolved single-photon detection with maximum-likelihood analysis enables the location of the biomolecule to be determined. Diffusional transport of the molecules is found to be slowed within the nanochannel, and this facilitates fluidic trapping and/or prolonged measurements on individual biomolecules. Our goal is to actively control the fluidic transport to achieve rapid delivery of each new biomolecule to the sensing zone, following the completion of measurements, or the photobleaching of the prior molecule. We have used computer simulations that include photophysical effects such as triplet crossing and photobleaching of the labels to design control algorithms, which are being implemented in a custom field-programmable-gate-array circuit for the active fluidic control.
Developments of high speed motor drive have been described. A switched reluctance motor has been designed for 2kW output at a rotational speed of more than 100,000r/min. A test machine has been constructed based on th...
详细信息
ISBN:
(纸本)9781424419050
Developments of high speed motor drive have been described. A switched reluctance motor has been designed for 2kW output at a rotational speed of more than 100,000r/min. A test machine has been constructed based on the design. The iron parts are fabricated by 6.5% silicon steel, i.e., low iron loss material. The rotational speed of 150,000r/min is reported experimentally. Fast and accurate controller has been developed using field programmable gate array device.
This paper presents the designing and implementation of a novel bit serial Least Mean Square adaptive filter based on a specially designed bit stream triangular compressor multiplier. The Architecture is used for proc...
详细信息
ISBN:
(纸本)9780769531144
This paper presents the designing and implementation of a novel bit serial Least Mean Square adaptive filter based on a specially designed bit stream triangular compressor multiplier. The Architecture is used for processing bit serial data in communication systems. The efficiently designed bit stream multiplier is the key performance factor in terms of area and power consumption.
暂无评论