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1.562 Gb/s phase-encrypted secure communication

IET OPTOELECTRONICS 2008年第5期2卷 201-208页

作者： Ajmal, T. Walker, S. D. Univ Essex Dept Comp & Elect Syst Engn Colchester CO4 3SQ Essex England

A field programmable gate array (FPGA)-based physical layer phase-encryption technique suitable for applications in high-speed passive optical networks is presented. The physical layer ciphering technique is based on a combination of multilevel phase shift keying (PSK) modulation and binary differential PSK. A mathematical model of the system is first derived and numerical simulations are obtained using Mathematica. Expressions for the probability of error for both a legitimate and eavesdropping receiver are derived and evaluated numerically. The results from experimental implementation using high-speed phase modulators and FPGAs are also given to further prove the efficacy of the presented technique. The macroscopic cryptography technique offers completely opaque communication over trans-oceanic distances, gigabit date rates and multiple wavelengths.

关键词： Data security Cryptography theory field programmable gate array phase-encrypted secure communication binary differential PSK error probability telecommunication security FPGA Logic and switching circuits Logic circuits passive networks cryptography high-speed passive optical networks error statistics Cryptography multilevel phase shift keying modulation mathematics computing optical fibre networks high-speed phase modulator bit rate 1.562 Gbit/s field programmable gate arrays macroscopic cryptography technique phase shift keying optical receivers eavesdropping receiver Optical fibre networks Optical communication equipment physical layer ciphering technique Mathematica Other topics in statistics

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FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field

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JOURNAL OF SYSTEMS ARCHITECTURE 2008年第12期54卷 1077-1088页

作者： Li, Hao Huang, Jian Sweany, Philip Huang, Dijiang Univ N Texas Dept Comp Sci & Engn Denton TX 76203 USA Univ Cent Florida Sch Elect Engn & Comp Sci Orlando FL 32816 USA Arizona State Univ Dept Comp Sci & Engn Tempe AZ 85287 USA

Elliptic curve cryptography (ECC) and Tate pairing are two new types of public-key cryptographic schemes that become popular in recent years. ECC offers a smaller key size compared to traditional methods without sacrificing Security level. Tate pairing is a bilinear map commonly used in identity-based cryptographic schemes. Therefore, it is more attractive to implement these schemes by using hardware than by using software because of its computational expensiveness. In this paper, we propose field programmable gate array (FPGA) implementations of the elliptic curve point Multiplication in Galois field GF(2(283)) and Tate pairing computation in GF(2(283)). Experimental results demonstrate that, compared with previously proposed approaches, Our FPGA implementations of ECC and Tate pairing can speed up by 31.6 times and 152 times, respectively. (c) 2008 Elsevier B.V. All rights reserved.

关键词： field programmable gate array Elliptic curve cryptography Tate pairing Parallel processing Galois field arithmetic

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Sub-Microsecond Ultra-Wideband Transceiver for Time-Critical Wireless Sensor Networks

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FREQUENZ 2008年第7-8期62卷 191-194页

作者： Seifarth, Chnstoph Jurenz, Tim Scholl, Gerd Helmut Schmidt Univ Univ Fed Armed Forces Hamburg Inst Elect Measurement Engn D-22039 Hamburg Germany

In wireless sensor networks (WSN) for time-critical applications a fast transmission of sensor data is required for proper system operation. This paper presents an ultra-fast ultra-wideband (UWB) transceiver for sub-microsecond communication in time-critical WSN. Sensor data is encoded in packets of one byte plus start and stop bits and transmitted with a data rate of 100 Mbit/s. With high-speed analog to digital conversion and digital signal processing less than 200 ns are required for data transmission and reception with possible data transmission every 120 ns. Circuit design and operating principle of the transceiver are explained and measurement results provided to prove its functionality.

关键词： Ultra-Wideband Wireless Sensor Network Transceiver field programmable gate array Sub-Real Time Communication

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Microelectronic implementations of fractional order integro-differential operators

Microelectronic implementations of fractional order integro-...

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ASME International Design Engineering Technical Conferences/Computers and Information in Engineering Conference

作者： Santamaria, Guillermo E. Valverde, Jose V. Perez-Aloe, Raquel Vinagre, Bias M. Univ Extremadura Sch Ind Engn E-06071 Badajoz Spain

ISBN: (纸本)9780791848067

For practical applications, the fractional order integral and differential operators require to be approximated as stable, causal, minimum-phase integer order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that an approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, field programmable gate arrays (FPGAs), Switched Capacitors Circuits (SCCs), and field programmable Analog arrays (FPAAs) are used in this paper for the implementation of a fractional order integrator, previously approximated by the recursive Oustaloup's method. The fundamentals of the devices, as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.

关键词： fractional order operator field programmable gate array field programmable Analog array Switched Capacitor active filter

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An Implementation of 2D Locally Coupled Relaxation Oscillators on an FPGA for Real-time Autowave Generation

An Implementation of 2D Locally Coupled Relaxation Oscillato...

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11th International Workshop on Cellular Neural Networks and Their Applications

作者： Yeniceri, Ramazan Yalcin, Muestak E. Istanbul Tech Univ Fac Elect & Elect Engn Dept Elect & Commun Engn TR-34469 Istanbul Maslak Turkey

ISBN: (纸本)9781424420896

This paper introduces a digital implementation of a new simple programmable autowave generator network on a field programmable gate array (FPGA). The network is a two dimensional reaction-diffusion Cellular Neural Network which consists of relaxation oscillators. The introduced implementation successfully simulates 25,600 neurons in real-time with novel Cellular Neural Processing Network architecture which uses floating-point number format. The implementation allows simulating the network with high numeric resolution and real-time monitoring of the evolution of autowaves. This FPGA implementation of the network provides a suitable platform to explore spatiotemporal behavior and to implement wave computing algorithms.

关键词： CNNs Cellular Wave Computing field programmable gate array Autowaves Relaxation oscillators

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Electrokinetic Delivery of Single Fluorescent Biomolecules in Fluidic Nanochannels

Electrokinetic Delivery of Single Fluorescent Biomolecules i...

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Conference on Biosensing

作者： Davis, Lloyd M. Canfield, Brian K. Li, Xiaoxuan Hofmeister, William H. Shen, Guoqing Lescano-Mendoza, Isaac P. Bomar, Bruce W. Wikswo, John P. Markov, Dmitry A. Samson, Philip C. Daniel, Claus Sikorski, Zbigniew Robinson, William N. Univ Tennessee Inst Space Ctr Laser Applicat Tullahoma TN 37388 USA Vanderbilt Univ Vanderbilt Inst Integrat Biosyst Nashville TN 37235 USA Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9780819472557

We describe the fabrication of sub-100-nanometer-sized channels in a fused silica lab-on-a-chip device and experiments that demonstrate detection of single fluorescently labeled proteins in buffer solution within the device with high signal and low background. The fluorescent biomolecules are transported along the length of the nanochannels by clectrophoresis and/or electro-osmosis until they pass into a two-focus laser irradiation zone. Pulse-interleaved excitation and time-resolved single-photon detection with maximum-likelihood analysis enables the location of the biomolecule to be determined. Diffusional transport of the molecules is found to be slowed within the nanochannel, and this facilitates fluidic trapping and/or prolonged measurements on individual biomolecules. Our goal is to actively control the fluidic transport to achieve rapid delivery of each new biomolecule to the sensing zone, following the completion of measurements, or the photobleaching of the prior molecule. We have used computer simulations that include photophysical effects such as triplet crossing and photobleaching of the labels to design control algorithms, which are being implemented in a custom field-programmable-gate-array circuit for the active fluidic control.

关键词： Single-molecule spectroscopy single-molecule trapping nanofluidics nanochannel photon counting lab-on-a-chip field programmable gate array biosensing

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Basic Characteristics of 150,000r/min Switched Reluctance Motor Drive

Basic Characteristics of 150,000r/min Switched Reluctance Mo...

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General Meeting of the IEEE-Power-and-Energy-Society

作者： Kozuka, Satoru Tanabe, Norimasa Asama, Junichi Chiba, Akira Tokyo Univ Sci Fac Sci & Technol Dept Elect Engn Chiba 2788510 Japan

ISBN: (纸本)9781424419050

Developments of high speed motor drive have been described. A switched reluctance motor has been designed for 2kW output at a rotational speed of more than 100,000r/min. A test machine has been constructed based on the design. The iron parts are fabricated by 6.5% silicon steel, i.e., low iron loss material. The rotational speed of 150,000r/min is reported experimentally. Fast and accurate controller has been developed using field programmable gate array device.

关键词： field programmable gate array high speed motor switched reluctance motor

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LMS Bit Stream Adaptive filter Design

LMS Bit Stream Adaptive filter Design

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UKSim 10th International Conference on Computer Modelling and Simulation (EUROSIM/UKSim)

作者： Perwaiz, Aqib Khan, Shoab A. Natl Univ Sci & Technol Coll E&ME Rawalpindi Pakistan Natl Univ Sci & Technol Coll E&ME Dept Comp Engn Rawalpindi Pakistan

ISBN: (纸本)9780769531144

This paper presents the designing and implementation of a novel bit serial Least Mean Square adaptive filter based on a specially designed bit stream triangular compressor multiplier. The Architecture is used for processing bit serial data in communication systems. The efficiently designed bit stream multiplier is the key performance factor in terms of area and power consumption.

关键词： field programmable gate array digital receiver direct digital frequency synthesizer multirate signal processing least mean Square

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Design of an FPGA-Based Real-Time Simulator for Electrical System

Design of an FPGA-Based Real-Time Simulator for Electrical S...

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13th International Power Electronics and Motion Control Conference

作者： Bahri, I. Naouar, M-W. Monmasson, E. Slama-Belkhodja, I. Charaabi, L. LSE ENIT BP 37 Tunis Le Belvedere 1002 Tunisia SATIE IUP GEII Cergy Pontoise France

ISBN: (纸本)9781424417414

This paper deals with a Real-Time Simulation (RTS) able to accurately reproduce an electrical system in real-time. The RTS proposed architecture is written in VHDL and implemented in a field programmable gate array (FPGA) device. Multi-sampling approach is adopted allowing a real-time functioning with different time-steps and different operating conditions with minimized lost of accuracy. The proposed concept is illustrated by the RTS of each of a three-phase RLE load performed with a very short time step of 2.5 mu s, an inverter, the measurement system and the hysteresis current controllers. Comparison with experimental results shows the high performances of this RTS.

关键词： Electrical system Real-Time Simulation multi-sampling field programmable gate array

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HIGH THROUGHPUT JPEG2000 COMPATIBLE ENCODER FOR HIGH DYNAMIC RANGE IMAGES

HIGH THROUGHPUT JPEG2000 COMPATIBLE ENCODER FOR HIGH DYNAMIC...

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15th IEEE International Conference on Image Processing (ICIP 2008)

作者： Hassan, Firas Carletta, Joan Univ Akron Dept Elect & Comp Engn Akron OH 44325 USA

ISBN: (纸本)9781424417650

This paper describes a high throughput encoder for high dynamic range (HDR) images that is compatible with the JPEG2000 engine. A nine-level Reinhard-like tone mapping operator is used to calculate a local illumination estimate around each pixel in the image. Both, the local illumination estimate and the tone mapped pixel streams are sent to the JPEG2000 engine for compression. When tested with HDR images and video, the encoder gave high quality output images with high peak signal-to-noise ratios for a compression rate of 4.8 bits per pixel (bpp). The encoder was implemented on a field programmable gate array (FPGA), and has high enough throughput to support a system processing 1024x768 images of 96 bpp at a rate of 60 frames per second.

关键词： high dynamic range local tone mapping operators field programmable gate array JPEG2000

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