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High-level synthesis assisted, low-latency, area- and power-optimized FPGA implementation of MUSIC algorithm for direction-of-arrival estimation

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SUSTAINABLE ENERGY TECHNOLOGIES AND ASSESSMENTS 2023年 57卷

作者： Sikka, Prateek ST Microelect Greater Noida Uttar Pradesh India

For multiple signal-processing applications, estimating the target's speed, distance, and elevation angle by using applications running in real time and consequently, fast data rates is important. Custom hardwares, such as field programmable gate arrays (FPGAs), are often used to prototype and deploy such signal-processing algorithms. Multiple signal classification (MUSIC) is typically used for direction-of-arrival (DOA) estimation. It involves complex mathematical operations such as covariance matrix computation, eigen value decomposition, and peak value search for signal values. With a novel high-level synthesis (HLS)-based design approach that optimizes the bit widths for the eigen value decomposition logic, this study presents an area and speed-optimal implementation of MUSIC algorithm on FPGA. The final implementation involving the covariance matrix computation, eigen value decomposition, and peak search was implemented on Xilinx Zynq (XC7Z020) FPGA. Because of its optimum bit widths, area utilization was minimized and operation frequency on the target FPGA was maximized. The proposed design works in real time to estimate the DOA in less than 1.7 mu s (15 % faster than reported values) and uses up to 30 % less resources on the target FPGA compared with other reported implementations.

关键词： Direction of arrival field programmable gate array High-level synthesis Multiple signal classification

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Load evaluation of campus football match based on microprocessor and IoT wearable equipment

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MICROPROCESSORS AND MICROSYSTEMS 2021年 81卷 103778-103778页

作者： Xu, Yetong Hu, Wenwu Tianshui Normal Univ Sch Sports & Hlth Tianshui 741000 Gansu Peoples R China Kunming Univ Phys Culture Inst Kunming 650000 Yunnan Peoples R China

Physiological and clinical and translation tools, the wearable device of semiconductor technology equipped with the convergence prediction of health analysis to advanced sports. Test and physical performance, physiological condition, biochemical composition, and subsequent application of indicators associated with mental warning players, development plans, as indicated by the physician or training teams, surrounding player?s performance, improve the protocol?s agreement, reduce the risk of injury. Provide an understanding of sports medicine wearable sensors. Commercial devices will include those described in the scientific literature. The primary purpose is to provide wearable technology to assess the biomechanical and physiological parameters of athletes. The second purpose of, the usefulness of this technology is, to a certain extent, it?s streaming players in various sports fields between the performances of the joint research, academic research groups, sports medicine clinic, and sports teams. It is to identify opportunities. Companion, the wisdom of monitoring biochemical indicators and the player of the wearable use.

关键词： Load evaluation Wearable electronic equipment field programmable gate array Football

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Image and video processing on FPGAs: An Exploration Framework for Real-Time Applications

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IFAC Proceedings Volumes 2010年第24期43卷 54-59页

作者： Zied El Hadhri Carlos Valderrama Paulo da Cunha Possa University of Mons Department of Electronics and Microelectronics Mons 7000 Belgium (Tel: +32-6537-4222)

This work presents a design framework for real-time image and video processing enabling exploration and evaluation of different processing techniques. The goal of our educational approach is to develop a flexible and easily customizable environment for prototyping different processing techniques on field programmable gate arrays (FPGAs), targeting specific applications. In this paper we give an overview of different requirements and techniques of video processing featuring FPGAs. Three real-time video processing algorithms were combined to show the advantages and characteristics of our approach. Within the framework, the modules running in parallel can be easily swapped at run-time according to the application specific needs.

关键词： Video processing field programmable gate array embedded systems hardware description language object tracking pattern detection

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A high throughput hardware architecture for deblocking filter in HEVC

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SIGNAL PROCESSING-IMAGE COMMUNICATION 2022年 100卷 116517-116517页

作者： Kopperundevi, P. Prakash, Matcha Surya Ahamed, Shaik Rafi Natl Inst Technol Calicut Calicut Kerala India Indian Inst Technol Guwahati Gauhati India

This paper presents a high throughput hardware architecture for deblocking filter in high efficiency video coding (H.265/HEVC) standard. The architecture uses an efficient hybrid pipelining and parallel processing techniques for intra encoder. A single edge filter is designed to process both horizontal and vertical filtering of pixels one after the other respectively. In our proposed architecture, the video frame is divided into 32 x 32 blocks and each block is processed by splitting them into blocks of 8 x 32 pixels in a pipelined manner. Parallel processing is employed for filtering the edges which helped in improving the throughput by decreasing the processing clock cycles. It has been observed that the largest coding tree unit block that the hardware architecture can process is 64 x 64 pixels and can be achieved in 64 clock cycles. Synthesis results of the Verilog design for the proposed architecture using application specific integrated circuit 180 nm standard cell library shows that it consumes 102k 2-input NAND gates and can work at a maximum clock frequency of 250 MHz. The proposed design is capable of supporting 8k ultra high definition video sequences at 322 Frames Per Second (fps) which is the best among the existing present-day architectures.

关键词： Deblocking filter H.265/HEVC Pipelining Parallel processing Application specific integrated circuit field programmable gate array

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Multi-rate Real Time Hybrid Simulation operated on a flexible LabVIEW real-time platform

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ENGINEERING STRUCTURES 2021年 239卷 112308-112308页

作者： Waldbjoern, P. Jacob Maghareh, Amin Ou, Ge Dyke, J. Shirley Stang, Henrik Tech Univ Denmark Dept Mech Engn Niels Koppels 404 DK-2800 Lyngby Denmark Tech Univ Denmark Dept Civil Engn Brovej 118 DK-2800 Lyngby Denmark Purdue Univ Lyles Sch Civil Engn 550 Stadium Mall Dr W Lafayette IN 47907 USA

This paper presents a real-time hybrid simulation (RTHS) strategy where the numerical and experimental substructures are executed at two different rates to optimize computational resources while maintaining an effective actuator control. The concept is referred to here as multi-rate real-time hybrid simulation (mrRTHS), and this approach is intended to enable low-cost RTHS by facilitating testing in the case of limited computational resources. Operated on a Laboratory Virtual Engineering Workshop (LabVIEW) real-time target, the mrRTHS concept is demonstrated through both a single- and multipledegree-of-freedom (SDOF) and (MDOF) mass-springdamper system. The numerical substructure generates a displacement signal with a coarse time step of Delta t. Using the current and three previous displacement data points, a finer control signal is defined with a time step of delta t, using a third-order polynomial algorithm referred to here as the polynomial fitting extrapolator. Both the numerical substructure and polynomial fitting extrapolator is executed with a sampling rate of Delta t by an on-board single-core processor-referred to here as the digital signal processor (DSP). Through a field-programmable gate array (FPGA) the control signal is compensated and transmitted to the transfer system through an I/O module with a sampling rate of 1 kHz (i.e. delta t = 0.001 sec). The ratio between Delta t and delta t are an integer-referred to here as the execution ratio. For an execution ratio of 1:5 and 1:10 the system performance is evaluated against a numerical model of the emulated structure-referred to here as the reference structure. For both the SDOF and MDOF system, a good correlation between the mrRTHS and reference is achieved with execution ratios of 1:5 and 1:10. When changing the execution ratio from 1:5 to 1:10, approximately 50% reduction of the required computational resources on the DSP is achieved.

关键词： Real-time hybrid simulation Hardware-in-the-loop Performance evaluation Experimental substructure Numerical substructure field programmable gate array

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An Embedded FPGA Architecture for Real-Time Model Predictive Control

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IFAC-PapersOnLine 2020年第2期53卷 7833-7838页

作者： Hussain I. Khajanchi Joseph N. Bruno Ambrose A. Adegbege Department of Electrical and Computer Engineering The College of New Jersey 2000 Pennington Road Ewing NJ 08628

We develop a custom hardware architecture for real-time implementation of embedded Model Predictive Control (MPC) on a field programmable gate array (FPGA). We propose a novel modular framework that allows for easy and rapid prototyping of control with capability for analog-to-digital conversion, numerical scaling, and digital-to-analog conversion. We demonstrate the effectiveness of the proposed framework for real-time control on a quadruple water tank system.

关键词： Embedded Model Predictive Control Primal-Dual algorithm Real-Time Control field programmable gate array Quadruple Tank System

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Hardware Co-Simulation of the BPSK and QPSK Systems on FPGA

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IFAC Proceedings Volumes 2012年第7期45卷 299-304页

作者： Silvana POPESCU Aurel GONTEAN Georgeta BUDURA Applied Electronics Department Faculty of Electronics and Telecommunications Politehnica University of Timisoara Timisoara Romania. Telecommunication Department Faculty of Electronics and Telecommunications Politehnica University of Timisoara Timisoara Romania.

The application of FPGAs (field programmable gate array) became an important issue in designing electronic systems. Also, the flexibility and performance offered by reconfigurable computing shorts the development time required for implementing digital signal processing solutions using FPGAs. In this paper, we present original hardware designs of the BPSK and QPSK systems, using Matlab/Simulink environment, System Generator and Xilinx ISE, in order to verify the functionality of the systems in hardware which speeds up the simulations. The capabilities of the Spartan 3E board are also compared with previous reported results.

关键词： demodulation Digital Signal Processing field programmable gate array hardware modulation phase modulation Reconfigurable Computing simulation

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Multi-hardware Real-time Simulator Resource Optimization Configuration Method

International Core Journal of Engineering

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International Core Journal of Engineering 2023年第11期9卷 71-75页

作者： Wenbin Mu Hao Wu

This article uses the subway traction power supply model as a simulation model to study the efficient and accurate real-time simulation of power systems with limited computing resources and real-time constraints. It focuses on the resource optimization configuration method for multi-hardware real-time simulators. Firstly, the article distinguishes the tasks suitable for different hardware based on their different computing characteristics, the generality of CPU, and the inherent high parallelism and stronger computing capabilities of FPGA. Then, it adopts a physics-decoupled method to perform fine-grained partitioning of the resource occupation rate required for processing tasks on each hardware, so that each module can operate with the minimum resource occupation rate on the hardware, maximizing hardware resource savings and computational *** multi-level parallel real-time simulation architecture is formed through the coordination allocation of the coarse-grained and fine-grained partitioned model on the hardware, from hardware level, module level, to element level.

关键词： Real-time Simulator field programmable gate array Resource Optimization Allocation

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An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2021年第4期30卷

作者： Iqbal, Muhammad Mazher Parvez, Husain Hussain, Fasahat Rashid, Muhammad Karachi Inst Econ & Technol Karachi 75190 Pakistan Digitek Engn Karachi Pakistan Umm Al Qura Univ Coll Comp & Informat Syst Comp Engn Dept Mecca Saudi Arabia

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF++. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF++. It is found through experimental results that an ASIF++ is 4-9% area-efficient and requires 36% lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2-5 circuits. It also achieves 34-53% area saving as compared to a traditional FPGA.

关键词： Application specific FPGA reconfigurable ASIC NPN SRAM-Table sharing field programmable gate array reconfiguration overheads

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A Disturbance Suppression Zeroing Neural Network for Robust Synchronization of Chaotic Systems and Its FPGA Implementation

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INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS 2022年第14期32卷 2250210-2250210页

作者： Chen, Weijie Jin, Jie Chen, Chaoyang Yu, Fei Wang, Chunhua Hunan Univ Sci & Technol Sch Informat & Elect Engn Xiangtan 411201 Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Peoples R China Hunan Univ Sch Comp Sci & Elect Engn Changsha 410082 Peoples R China

The synchronization of chaotic systems plays an extremely imperative and fundamental role in the fields of science and engineering. Notably, various external noise disturbances have a great impact on the synchronization of chaotic systems because chaotic systems are quite sensitive to the change of their initial values. Consequently, the robustness of chaotic system synchronization must be considered in practical applications. From this viewpoint, the present paper proposes a disturbance suppression zeroing neural network (DSZNN) for robust synchronization of chaotic and hyperchaotic systems, and the DSZNN is implemented on field programmable gate array (FPGA) for further hardware validation. The distinctive features of the proposed DSZNN controller have the ability to suppress disturbance with faster convergent speed and higher accuracy compared with super-exponential zeroing neural network (SEZNN) and conventional zeroing neural network (CZNN). Moreover, theoretical analysis, comparative numerical simulations and hardware validations for the synchronization of a hyperchaotic system are presented to demonstrate the superior performance of the proposed DSZNN.

关键词： Zeroing neural network chaotic system synchronization field programmable gate array noise disturbances

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