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Designing and Implementing a Lightweight WSN MAC Protocol for Smart Home Networking Applications

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2017年第3期26卷 1750043-1750043页

作者： Chen, Ching-Han Lin, Ming-Yi Lin, Wen-Hung Natl Cent Univ Dept CSIE Machine Intelligence & Automat Technol MIAT Lab 300 Jhongda Rd Taoyuan 32001 Taiwan

Wireless sensor networks (WSNs) represent a promising solution in the fields of the Internet of Things (IoT) and machine-to-machine networks for smart home applications. However, to feasibly deploy wireless sensor devices in a smart home environment, four key requirements must be satisfied: stability, compatibility, reliability routing, and performance and power balance. In this study, we focus on the unreliability problem of the IEEE 802.15.4 WSN medium access control (MAC), which is caused by the contention-based MAC protocol used for channel access. This problem results in a low packet delivery ratio, particularly in a smart home network with only a few sensor nodes. In this paper, we first propose a lightweight WSN protocol for a smart home or an intelligent building, thus replacing the IEEE 802.15.4 protocol, which is highly complex and has a low packet delivery ratio. Subsequently, we describe the development of a discrete event system model for the WSN by using a GRAFCET and propose a development platform based on a reconfigurable FPGA for reducing fabrication cost and time. Finally, a prototype WSN controller ASIC chip without an extra CPU and with our proposed lightweight MAC was developed and tested. It enhanced the packet delivery ratio by up to 100%.

关键词： field programmable gate array lightweight MAC wireless sensor network ZigBee

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Scalable Control System Based on Matrix of Controllers – Preliminary Results

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IFAC-PapersOnLine 2022年第4期55卷 183-188页

作者： Chaber Patryk Wojtulewicz Andrzej Warsaw University of Technology Institute of Control and Computation Engineering ul. Nowowiejska 15/19 00-665 Warsaw Poland

The work aims to develop an original software and hardware structure for the regulation of fast dynamic processes. The structure will allow simultaneous predictive regulation of many processes with independent dynamics. Designing the matrix of regulators managed by a specialized subsystem allows the user to use advanced regulation algorithms within a single embedded system, which will improve the design and development processes of an industrial regulation system. The presented innovative approach will allow the reproduction of many control scenarios such as parallel regulation of several processes or securing the regulation of a critical process by a redundancy of controllers.

关键词： field programmable gate array Model Predictive Control Matrix of Controllers

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Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA

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MEHRAN UNIVERSITY RESEARCH JOURNAL OF ENGINEERING AND TECHNOLOGY 2015年第4期34卷 441-446页

作者： Kundi, Dur-E-Shahwar Aziz, Arshad Natl Univ Sci & Technol Dept Elect Engn Islamabad Pakistan

This work presents an efficient implementation of the AES (Advance Encryption Standard) based on T-box/T-1-box design for both the encryption and decryption on FPGA (field programmable gate array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption.

关键词： Advance Encryption Standard BRAM field programmable gate array T-Box/T-1-Box

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Fault Tolerant Reconfigurable System with Dual-Module Redundancy and Dynamic Reconfiguration

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Journal of Electronic Science and Technology 2011年第2期9卷 167-173页

作者： Qi-Zhong Zhou Xuan Xie Jing-Chen Nan Yong-Le Xie Shu-Yan Jiang School of Automation Engineering University of Electronic Science and Technology of ChinaChengdu 611731China Intel Corporation Chengdu 611731China School of Physics and Electronic Engineering Yibin UniversityYibin 644000China

To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable technique of field programmable gate array（FPGA）. This system contains detection and backup alternative functions,that is,the self-detection and self-healing functions can be completed,and consequently a system design with low hardware redundancy and high resource utilization can be achieved successfully. So it can not only detect fault but also repair the fault effectively after failure. Hence,this method is especially practical to the dynamically reconfigurable computers based on FPGAs. Design methodology has been verified by Virtex-4 FPGA on Xilinx Ml403 development platform.

关键词： Dependable computers fault-tolerant field programmable gate array self-detection single event upsets

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Design for the system of high-speed data transmission and data pre-processing for synthetic aperture radar imaging based on the system-on-a-programmable-chip

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JOURNAL OF ENGINEERING-JOE 2019年第20期2019卷 6537-6540页

作者： Hu, Shankang Liu, Xiaoning Xie, Yizhuang Hu, Shanqing Li, Bingyi Beijing Inst Technol Sch Informat & Elect Radar Res Lab Beijing 100081 Peoples R China Beijing Inst Technol Beijing Key Lab Embedded Real time Informat Proc Beijing 100081 Peoples R China DFH Satellite Co Ltd Beijing 100081 Peoples R China

For the chirp scaling algorithm of synthetic aperture radar imaging, an efficient transmission of a large volume of data is indispensable. Prior to imaging, there is a requirement for appropriate pre-processing of the echo signal by digital down conversion (DDC). The DDC module has to remove the carrier, having an appropriate filtering processing and down-sampling processing. No matter what imaging mode is chosen, such as the stripmap mode, spotlight mode, and sliding spotlight, the needs of the whole imaging system are matched by setting a series of configurations about this pre-processing module and this transmission module. The system-on-a-programmable-chip constituted by the Advanced RISC Machine and field programmable gate array (FPGA) is the perfect experimental platform to test the performance of this system. Some of the algorithms, which are more feasible for this specific project for pre-processing in Maltab, were transplanted to FPGA using the VHSIC Hardware Description Language for functional verification. Finally, the processing results in Matlab were compared with this system to find the difference. At the same time, the time that elapsed from the 2 GB original data entering the system to the time the processed results were completely returned to the PC was also counted.

关键词： radar imaging synthetic aperture radar system-on-chip field programmable gate array transmission module pre-processing module imaging system spotlight mode stripmap mode down-sampling processing DDC module chirp scaling algorithm system-on-a-programmable-chip synthetic aperture radar imaging data pre-processing high-speed data transmission

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Rotator on Chip (RoC) Design Based on Ring Topological NoC

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Procedia Computer Science 2015年 45卷 540-548页

作者： Adesh Kumar Lopamudra Baruah Amit Sabu Department of Electronics & Instrumentation Engineering University of Petroleum & Energy Studies Dehradun India Graduate Student Department of Electronics &Instrumentation Engineering University of Petroleum & Energy Studies Dehradun India

The paper presents the ring based Network on Chip (NoC) structure design and modeling in Hardware Description Language (HDL). The network configuration is chosen for 65536 nodes, which is synchronized with same clock pulse. The functionality of each node is checked in Modelsim 10.1b software. The interprocess communication among nodes in verified using Virtex-5 FPGA. The priority of the nodes is assigned using FIFO logic, which is integrated with the NoC chip. The NoC architecture is based on token ring based network concept, called Rotator-on Chip (RoC). The design and modeling is done in Xilinx 14.2 ISE using VHDL programming language and synthesized on Digilent manufactured FPGA, with the target device, xc5vlx20t-2-ff323, Virtex-5. Hardware and timing parameters are extracted from the synthesized results and maximum frequency is found 535.733 MHz and memory utilization is 263208 kB.

关键词： Rotator on Chip Network on Chip Hardware Description Language Very large Scale of Integration field programmable gate array

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Fast explicit MPC with multiway trees

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IFAC Proceedings Volumes 2011年第1期44卷 1356-1361页

作者： M. Mönnigmann M. Kastsian Automatic Control and Systems Theory Ruhr-Universität Bochum 44801 Bochum Germany

Abstract We show that explicit model predictive control (EMPC) laws, or more generally continuous piecewise affine control (PWA) laws on polyhedra, can be represented by multiway trees with two important features: (i) Their height can be reduced arbitrarily by increasing their order m (i.e. the number of binary tree nodes hidden in each multiway node). (ii) A multiway node can be evaluated as fast as a binary node with a simple but massively concurrent (or “parallel”) procedure for m ≫ 1. As a result the control law evaluation can be evaluated considerably faster than with a binary tree. Furthermore, we show that a multiway tree representation of an EMPC control law can be derived from the corresponding binary tree representation with a simple algorithm. Finally, we demonstrate that programmable logic devices are ideally suited for an implementation. First tests show that EMPC control laws with several thousand hyperplanes can be evaluated in a few clock cycles on compact, low-cost, low-power programmable logic devices.

关键词： predictive control explicit field programmable gate array piecewise affine

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Hybrid multilevel DC link inverter with reduced power electronic switches

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Energy Procedia 2017年 117卷 626-634页

作者： G Durga Prasad V Jegathesan P V V Rama Rao Shri Vishnu Engineering College for Women EEE Dept. Bhimavaram Andhra pradesh 534202 India

The employments of Multilevel DC Link Inverters offer dependable points of interest attributable to the expansion in the highest levels at the yield output voltage and are broadly acknowledged for industrial applications. The execution of these bores on high when contrasted with the routine conventional two-level inverters because of their drawbacks. Be that as it may, the expanded number of devices, complex PWM control, and voltage-adjusting issue are a portion of the hindrances. This paper goes for presenting another topology, which can perilously decrease the switch number by introducing a module called polarity generation module. This topology gives a DC voltage fit as a fiddle of a staircase which approximates the corrected state of a directed sinusoidal wave to the extension inverter, which thusly interchanges the extremity to deliver an AC voltage with low THD and switching loss. The topology is tested by adopting a choice of control techniques and enhanced execution of the proposed inverter contrasted with the overarching topologies. The FPGA has been selected to verify the proposed inverter with modulating technique due its advanced futures and computing facility. For validation, simulation and experimental results are offered.

关键词： field programmable gate array Multilevel DC Link Inverters Pulse Width Modulation sinusoidal pulse width modulation Total Harmonic Distortion

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Efficient AI Reasoning Model Based on FPGA

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Procedia Computer Science 2023年 228卷 1068-1076页

作者： Junyi Ran School of Big Data Chongqing Vocational College of Transportation Chongqing 402247 China

The artificial intelligence inference model is currently the best mathematical model based on artificial neural networks. The intelligent reasoning mode based on artificial intelligence has a large construction scale. In a completed inference, many multiplication and addition operations need to be completed. To establish an effective artificial intelligence inference model, its computational complexity is dozens or even more times higher than traditional artificial intelligence algorithms. This article focused on the research on the isomerization acceleration of FPGA (field programmable gate array). This article was looking for a method that reduces both system changes and migration, while maximizing the flexibility of FPGA programmability. In order to build on this foundation, a fast interface for fast computation using FPGA was designed. The characteristic of this project was that it could combine the FPGA acceleration platform with ordinary computers or servers, and could effectively utilize traditional computer software and toolchains. This article compared the computational time consumption between the inference model and the CPU. In the scale calculation logic scenario of the inference model designed in this article, it could achieve the same computing power as the CPU when processing 70000 multiplication calculations. The experimental results indicated that the increase in CPU computing power was greater than that of the inference model. This indicated that the larger the amount of computational data, the more significant the acceleration effect of the inference model in this article would be.

关键词： AI Reasoning Model Central Processing Unit field programmable gate array Graphics Processing Unit

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Selection of an Optimum Entropy Source Design for a True Random Number Generator

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Procedia Technology 2016年 25卷 598-605页

作者： Lakshmi Sreekumar P. Ramesh P G Scholar College of Engineering Munnar Idukki Pin 685612 India Associate professor College of Engineering Munnar Idukki Pin 685612 India

Random number generators are a vital component in many cryptographic algorithms and systems, such as generation of keys in secret key cryptography and public key cryptography. For cryptographic applications, True Random Number Generator utilizes unpredictability as the key component. Insufficient entropy produces predictable keys, so the major concern is to have a better entropy source. Entropy source which is based on a delay chain structure is presented in this paper. Here the randomness is generated by the timing differential existing between the clock and the data signal. In this design the delays are adjusted so that the data can be sampled at the limit of switching point The proposed design is very simple as it is based on a loop structure which does not contain any complex structures like Delay Locked Loop (DLL).

关键词： Entropy Metastability field programmable gate array

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