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FPGA-based methodology for depth-of-field extension in a single image

DIGITAL SIGNAL PROCESSING 2017年 70卷 14-23页

作者： Lopez-Ramirez, M. Ledesma-Carrillo, L. M. Cabal-Yepez, E. Botella, G. Rodriguez-Donate, C. Ledesma, Sergio Univ Guanajuato Div Ingn Campus Irapuato SalamancaAve Univ SN Guanajuato 38944 Mexico Univ Complutense Madrid Dept Arquitectura Comp & Automat Ave Complutense S-N E-28040 Madrid Spain

Computer vision applications rely upon high resolution images with extended depth of field (DoF). Most approaches contain arrays of lenses and computing intensive algorithms that must be calibrated every time, to reach in-focus images;however, by changing directly the system focal length, resolution and information are lost. Traditional methods consist in taking a great number of images varying the optical system pupil aperture, whereas, the post processing system demands a great amount of computational resources with long processing time and high implementation cost. In this work a novel methodology for DoF extension that applies a complex-amplitude mask during a single image pre-processing taken at full pupil aperture, and a Wiener filter for the image recovery without focalization errors, during post-processing, is introduced. An FPGA-based implementation shows the feasibility of the proposed methodology for real-time DoF extension. Obtained results demonstrate qualitatively and quantitatively the effectiveness of the proposed FPGA-based method, which offers a reconfigurable solution for online DoF extension on a single image, in real time. (C) 2017 Elsevier Inc. All rights reserved.

关键词： Complex-amplitude mask Extended depth of field field programmable gate array High-resolution imaging One single image processing Wiener filter

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Heavy-Ion Micro Beam and Simulation Study of a Flash-Based FPGA Microcontroller Implementation

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2017年第1期64卷 504-511页

作者： Evans, Adrian Ortega, Carlos Urbina Marinis, Kostas Costenaro, Enrico Laroussi, Houssem Obbe, Kay-Voss Magistrati, Giorgio Ferlet-Cavrois, Veronique IROC Technol F-38000 Grenoble France European Space Agcy NL-2200 AG Noordwijk Netherlands Helmholtzzentrum Schwerionenforsch GSI D-64291 Darmstadt Germany

Flash-based FPGAs are frequently used in space applications and it is now common for such designs to include a small microcontroller. In this paper, we present the results of a detailed study of two implementations of an ARM (R) Cortex (R)-M0+ processor. The first implementation uses a standard design flow while the second implementation is protected with RHBD techniques including TMR flip-flops. Both designs were tested using a heavy-ion micro-beam using a methodology which enables individual ions to be localized both in space and time. The rate of silent data corruption (SDC) was only reduced by 5x in the protected version. Many, but not all, of the error scenarios were reproduced using simulation based fault injection. Overall, the results suggest that the contribution of single event transients (SETs) can not be neglected and the results show the limitations of flip-flop based TMR.

关键词： Embedded systems embedded processor field programmable gate array radiation hardening reliability single event transient (SET) single event upset (SEU) single event

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Modified impedance source inverter for power conditioning system

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SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES 2017年第3期42卷 353-364页

作者： Suganthi, J. Rajaram, M. Govt Coll Engn Dept Elect & Elect Engn Tirunelveli 627007 India Anna Univ Madras 600025 Tamil Nadu India

Based on classical impedance source inverter concept, this paper presents a modified impedance source inverter controlled by different pulse width modulation control strategies for solar PV/battery-powered applications. A brief topology analysis, generalized discussion and design of impedance network elements are presented. Comparison with the classical impedance source inverter is presented. Using simulation, analytical results are presented that ensure stability. The proposed voltage type inverter has reduced inrush current at startup, less capacitor voltage stress and minimum inductor current ripples. DC link voltage boost, reduced total harmonic distortion of output current and voltage, better voltage gain and wide range of output voltage control can be achieved easily with improved power quality. Experimental set-up of the modified impedance source inverter with field programmable gate array (FPGA) controller has been constructed to ascertain the results.

关键词： Modified impedance source inverter power conditioning system cross conduction period modified space vector pulse width modulation field programmable gate array

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FPGA-based SOC for hardware implementation of a local histogram-based video shot detector

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2017年第4期25卷 3300-3318页

作者： Ben Abdelali, Abdessalem Krifa, Mohamed Nidhal Mtibaa, Abdellatif Univ Monastir Lab Elect & Microelect Monastir Tunisia

In this paper, we present a video application example and its implementation in a reconfigurable system-on chip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse hardware module versions corresponding to different quantization levels and architectural solutions for an LH-based shot detection system are presented. The developed modules have different hardware resource occupations and can be used in a dynamic way to allow flexible management of the target hardware system. They also show high execution time efficiency and can reach an important bandwidth that can support the most recent high-resolution video formats with a high rate of frames per second. A complete SOC-based demonstration for video summarization based on the LH is also developed. It includes the LH extraction, shot boundary detection, and key frame visualization.

关键词： Hardware implementation field programmable gate array system on chip partial dynamic reconfiguration real time local histogram shot boundary detection video summarization

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Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA

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IET COMPUTERS AND DIGITAL TECHNIQUES 2017年第4期11卷 149-158页

作者： Zhang, Hao Chen, Dongdong Ko, Seok-Bum Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N 5A9 Canada Intel Corp San Jose CA USA

In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look-up tables (LUTs), and 31.2% less flip-flops while having 4% faster clock frequency on Virtex-5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower-power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex-7 and Altera Arria-10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM-90 nm ASIC platform are reported.

关键词： field programmable gate arrays floating point arithmetic iterative methods floating-point multiplication field programmable gate array DSP blocks power-efficient iterative FP multiplier architecture single-precision operations double-precision operations Karatsuba algorithm pipeline registers Virtex-5 devices Altera Arria-10 devices Xilinx Virtex-7 ASIC platform

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A real-time near infrared image acquisition system based on image quality assessment

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2017年第1期13卷 103-120页

作者： Lee, Y. H. Khalil-Hani, M. Bakhteri, Rabia Nambiar, Vishnu P. Univ Teknol Malaysia Fac Elect Engn VeCAD Res Lab Utm Skudai 81310 Johor Bahru Malaysia

This paper presents a real-time image acquisition system with an improved image quality assessment module to acquire high-quality near infrared (NIR) images. Thermal imaging plays a vital role in a wide range of medical and military applications. The demand for high-throughput image acquisition and image processing has continuously increased especially for critical medical and military purposes where executions under real-time constraints are required. This work implements an NIR image quality assessment module, which utilizes improved two-dimensional entropy and mask-based edge detection algorithms. The effectiveness of the proposed image quality assessment algorithms is demonstrated through the implementation of a complete finger-vein biometric system. The proposed model is implemented as an embedded system on a field programmable gate array prototyping platform. By including the image quality assessment module, the proposed system is able to achieve a recognition accuracy of 0.87 % equal error rate, and can handle real-time processing at 15 frames/s (live video rate). This is achieved through hardware acceleration of the proposed image quality assessment algorithms via a novel streaming architecture.

关键词： Real-time image acquisition Image quality assessment field programmable gate array Biometrics Finger-vein

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RTL implementations and FPGA benchmarking of selected CAESAR Round Two authenticated ciphers

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MICROPROCESSORS AND MICROSYSTEMS 2017年 52卷 202-218页

作者： Diehl, William Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22033 USA George Mason Univ Cryptog Engn Res Grp Fairfax VA 22033 USA

Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs. The authenticated ciphers chosen for this research are the CAESAR Round Two variants of SCREAM, POET, Minalpher, and OMD. Ciphers are discussed from an engineering standpoint, and are compared and contrasted in terms of design features. To ensure conformity and standardization in evaluation, all four candidates are implemented with an identical version of the CAESAR Hardware API for authenticated ciphers. Functionally correct implementations of all four ciphers are realized, and results are compared against each other and previous results in terms of throughput, area, and throughput-to-area (TP/A) ratio. SCREAM is found to have the highest TP/A ratio of these four ciphers in the Virtex-6 FPGA, while Minalpher has the highest TP/A ratio in the Virtex-7 FPGA. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Authentication Cipher Cryptography Encryption field programmable gate array

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Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2017年第3期14卷 184-197页

作者： Lovelly, Tyler M. George, Alan D. Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp 330 Benton Hall Gainesville FL 32611 USA Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp 327 Larsen Hall Gainesville FL 32611 USA

Due to harsh and inaccessible operating environments, space computing presents many unique challenges and constraints that limit onboard computing performance. However, the increasing need for real-time sensor and autonomous processing, coupled with limited communication bandwidth with ground stations, is increasing onboard computing demands for next-generation space missions. Because currently available space-grade processors cannot satisfy this growing demand, research into various processors is conducted to ensure that potential new processors are based upon architectures that will best meet the computing needs of space missions. Device metrics are used to measure and compare the theoretical capabilities of processors based upon vendor-provided data and tools, enabling the study of large and diverse sets of architectures. Architectural tradeoffs are determined that can be considered when comparing or designing space-grade processors. Results demonstrate how onboard computing capabilities are increasing due to emerging architectures that support high levels of parallelism in terms of computational units, internal memories, and input/output resources;and that performance varies between applications, depending on the compute-intensive kernels used. Furthermore, the overheads incurred by radiation hardening are quantified and used to analyze low-power commercial-off-the-shelf processors for potential hardening and use in future space missions.

关键词： Commercial off the Shelf Space Missions Onboard Computing Performance Space Computing Sensor Technology Ground Station Central Processing Unit BAE Systems field programmable gate array Graphics Processing Unit

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Design and test of a new development FPGA board for mobile robot research

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2017年第2期25卷 1483-1494页

作者： Naji, Baligh Abdelmoula, Chokri Abbes, Karim Masmoudi, Mohamed Sfax Univ Natl Engn Sch Sfax Dept Elect Engn Sfax Tunisia

This paper presents the design and testing of a newly developed field programmable gate array (FPGA) board for mobile robot research. The idea consists of interfacing the FPGA to a 16-bit digital signal controller (dsPIC). This idea enables the FPGA designs to communicate with the dsPIC through the integration of per-written driver modules to be used in a wide variety of digital and analog peripheral modules. It also allows the use of a high-performance digital signal processing core in many signal processing-based mobile robot applications. The proposed FPGA board allows users to develop, test, and deploy quick and cost-effective complete design solutions to control the entire robot system in various applications without the need for external components.

关键词： Digital signal controller electronic design automation tools field programmable gate array robotics applications

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Model Predictive Control of an Underactuated Spacecraft with Two Reaction Wheels

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2017年第2期40卷 320-332页

作者： Petersen, Christopher D. Leve, Frederick Kolmanovsky, Ilya Univ Michigan Dept Aerosp Engn Ann Arbor MI 48109 USA US Air Force Res Lab Guidance Nav & Control Grp Albuquerque NM 87117 USA

This paper presents an application of model predictive control to the attitude dynamics of an underactuated spacecraft with two reaction wheels and zero angular momentum. Such a system cannot be stabilized by any smooth or continuous time-invariant feedback law. However, model predictive control has a remarkable ability to generate control laws that are discontinuous in the state and, as such, can be applied to this problem. The model predictive control formulation is analyzed in depth and shown to produce an asymptotically stabilizing controller, which is discontinuous and enforces constraints. Simulations on the full nonlinear model demonstrate that model predictive control can successfully control the attitude of an underactuated spacecraft when the attitude maneuvers are sufficiently small.

关键词： Spacecraft Attitude Spacecraft Models Model Predictive Control Feedback Control Attitude Stabilization Euler Angles Optimal Control Nonlinear Dynamics field programmable gate array Spacecraft Missions

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