检索结果-内蒙古大学图书馆

Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC

引用

IET CIRCUITS DEVICES & SYSTEMS 2011年第5期5卷 351-359页

作者： Malik, P. Slovak Acad Sci Inst Informat Bratislava 84507 Slovakia

Modified discrete cosine transform (MDCT) is used in many audio coding standards for time-to-frequency transformation of digital signals. It is one of the most computationally intensive operations in audio compression and decompression processes. In this study, optimised dedicated hardware architectures utilised in a highly scalable MDCT IP core are proposed to accelerate the forward/backward MDCT computation in MP3 audio coding standard. The MDCT IP core is pipelined, capable to compute both the forward and backward MDCT on the same hardware and it is optimised with field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC) technologies. The MDCT IP core is implemented to FPGA and ASIC, whereby the FPGA implementation used Xilinx Virtex-4 FPGA, while the ASIC implementation used AMS 350 nm CMOS standard cell library. The MDCT IP core is further optimised and implemented utilising UMC 90 nm CMOS low-power digital libraries and clock gating technique. As a result, power consumption and the area are reduced significantly. The proposed hardware architectures are optimised to achieve high computational speed with high precision, and therefore they are suitable for a lossless audio compression. In particular, high computational speed permits multichannel real-time acceleration of the forward and backward MDCT computation.

关键词： field-programmable gate arrays application-specific integrated circuit low-power ASIC backward modified discrete cosine transform Xilinx Virtex-4 FPGA size 350 nm forward modified discrete cosine transform low-power electronics AMS CMOS standard cell library size 90 nm digital signals time-to-frequency transformation CMOS low-power digital libraries discrete cosine transforms MP3 application specific integrated circuits lossless audio compression logic design IP core clock gating technique CMOS integrated circuits field programmable gate arrays clocks audio decompression audio coding standards audio coding

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of Asynchronous Processor on FPGA

引用

IEEE ACCESS 2022年 10卷 118370-118379页

作者： Shin, Ziho Oh, Myeong-Hoon Elect & Telecommun Res Inst ETRI Affiliated Inst Daejeon South Korea Honam Univ Dept Comp Engn Gwangju South Korea

Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA) that can fundamentally overcome the drawbacks of conventional synchronous circuit designs. We used commercial FPGAs and implemented an asynchronous MSP430 microprocessor using the proposed technique. We also introduce an interfacing architecture between the synchronous block memory and asynchronous core to support the congeniality of the commercial embedded processor and the asynchronous core. Furthermore, we analyze a compiler for MSP430 and adapt its result to achieve a high-level development environment for asynchronous MSP430. The experimental results showed that the asynchronous MSP430 consumes 62.3% less power than its synchronous counterpart and has significant fault tolerance compared to the synchronous MSP430 under unstable supply voltage conditions. Additionally, the asynchronous MSP430 emitted 13% less electromagnetic noise at the working frequency.

关键词： Asynchronous circuits field-programmable gate arrays microprocessors

来源：评论

学校读者我要写书评

暂无评论

An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

引用

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2010年第6期59卷 1663-1670页

作者： Szplet, Ryszard Klepacki, Kamil Mil Univ Technol PL-00908 Warsaw Poland

We present the design and test results of a new time-to-digital converter based on the cyclic pulse shrinking method and implemented in a field-programmable gate array (FPGA) device. The pulse shrinking is realized in a loop containing two complementary delay lines. The first line shrinks, and the second line stretches the duration time of a circulating pulse;hence, the length ratio of the lines determines the pulse-shrinking capability of the converter. This resolution control mechanism is different from the bias adjustment typically used in complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) pulse-shrinking elements. Two forms of representation of a measured time interval (the pulse width and the time interval between two pulses) are utilized in the described converter to improve the efficiency of resolution control. To diminish the jitter of the edges of a circulating pulse and, consequently, to increase the precision of the converter, a two-stage conversion is introduced. The first stage, having a low resolution, rapidly shortens the measured pulse, thus limiting the number of cycles, whereas the second stage provides a final high resolution within a narrow time interval range. The optimal resolution of the first conversion stage is theoretically derived. Mostly, the same logical resources of the FPGA device are utilized in both conversion stages;thus, the overall area overhead of the converter is reduced. The converter has a resolution of 42 ps and a measurement uncertainty of below 56 ps within the measurement range of 11.5 ns. The converter has been implemented in a general-purpose reprogrammable device Spartan-3 (Xilinx).

关键词： field-programmable gate arrays pulse shrinking time digitizer time-to-digital converter two-stage interpolation

来源：评论

学校读者我要写书评

暂无评论

Provably sublinear point multiplication on Koblitz curves and its hardware implementation

引用

IEEE TRANSACTIONS ON COMPUTERS 2008年第11期57卷 1469-1481页

作者： Dimitrov, Vassil S. Jarvinen, Kimmo U. Jacobson, Michael J., Jr. (Andy) Chan, Wai Fong Huang, Zhun Univ Calgary Dept Elect & Comp Engn Calgary AB T2N 1N4 Canada Aalto Univ Dept Signal Proc & Acoust FIN-02150 Espoo Finland Univ Calgary Dept Comp Sci Calgary AB T2N 1N4 Canada VIA Technol Beijing Peoples R China

We describe algorithms for point multiplication on Koblitz curves using multiple-base expansions of the form k = Sigma +/- tau(a) (tau - 1)(b) and k = Sigma +/- tau(a)(tau - mu)(b)(tau(2) - mu tau - 1)(c). We prove that the number of terms in the second type is sublinear in the bit length of k, which leads to the first provably sublinear point multiplication algorithm on Koblitz curves. For the first type, we conjecture that the number of terms is sublinear and provide numerical evidence demonstrating that the number of terms is significantly less than that of tau-adic nonadjacent form expansions. We present details of an innovative FPGA implementation of our algorithm and performance data demonstrating the efficiency of our method. We also show that implementations with very low computation latency are possible with the proposed method because parallel processing can be exploited efficiently.

关键词： elliptic curve cryptography field-programmable gate arrays Koblitz curves multiple-base expansions parallel processing sublinearity

来源：评论

学校读者我要写书评

暂无评论

Design of a Compact Sound Localization Device on a Stand-Alone FPGA-Based Platform

引用

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2016年第11期E99D卷 2682-2693页

作者： Kugler, Mauricio Tossavainen, Teemu Kuroyanagi, Susumu Iwata, Akira Nagoya Inst Technol Dept Comp Sci & Engn Nagoya Aichi 4668555 Japan Aalto Univ Sch Sci Dept Comp Sci & Engn Konemiehentie 2 Espoo 02150 Finland

Sound localization systems are widely studied and have several potential applications, including hearing aid devices, surveillance and robotics. However, few proposed solutions target portable systems, such as wearable devices, which require a small unnoticeable platform, or unmanned aerial vehicles, in which weight and low power consumption are critical aspects. The main objective of this research is to achieve real-time sound localization capability in a small, self-contained device, without having to rely on large shaped platforms or complex microphone arrays. The proposed device has two surface-mount microphones spaced only 20 mm apart. Such reduced dimensions present challenges for the implementation, as differences in level and spectra become negligible, and only time-difference of arrival (TDoA) can be used as a localization cue. Three main issues have to be addressed in order to accomplish these objectives. To achieve real-time processing, the TDoA is calculated using zero-crossing spikes applied to the hardware-friendly Jeffers model. In order to make up for the reduction in resolution due to the small dimensions, the signal is upsampled several-fold within the system. Finally, a coherence-based spectral masking is used to select only frequency components with relevant TDoA information. The proposed system was implemented on a field-programmable gate array (FPGA) based platform, due to the large amount of concurrent and independent tasks, which can be efficiently parallelized in reconfigurable hardware devices. Experimental results with white-noise and environmental sounds show high accuracies for both anechoic and reverberant conditions.

关键词： sound localization time difference of arrival compact device real-time field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

引用

IEEE TRANSACTIONS ON COMPUTERS 2017年第6期66卷 982-995页

作者： Ebrahimi, Zahra Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Tehran *** Iran

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in field-programmable gate arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of Reconfigurable Hard Logics (RHLs) and a small-input LUT. In the proposed architecture, we selectively turn off unused RHLs and/or LUTs within each logic block by employing a reconfigurable controller. By mapping a majority of logic functions to simple-design RHLs, PEAF is able to significantly improve power efficiency without deteriorating the performance. Experimental results over a comprehensive set of benchmarks (MCNC, IWLS'05, and VTR) demonstrate that compared with baseline four-LUT architecture, PEAF reduces the total static power and Power-Delay-Product (PDP), on average, by 24.5 and 21.7 percent, respectively. This is while the overall system performance is also improved by 1.8 percent. PEAF increases total area by 18.9 percent, however, it still occupies 22.1 percent less area footprint than the six-LUT architecture with 31.5 percent improvement in PDP.

关键词： field-programmable gate arrays static power SRAM dark silicon hard logic

来源：评论

学校读者我要写书评

暂无评论

From C to netlists: hardware engineering for software engineers?

引用

ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL 2002年第4期14卷 165-173页

作者： Alston, I Madahar, B BAE Syst Ctr Adv Technol Dept Syst Chelmsford CM2 8HN Essex England

The software programmable multiprocessor architecture has been employed extensively over the past two decades for embedded signal-processing applications. However, the increased complexity of such systems has, in many cases, required the use of hardware acceleration to meet the growing time-critical apsects of the design. Today's field-programmable gate arrays (FPGAs) offer an alternative or additional acceleration platform, especially to an application-specific integrated circuit (ASIC). However, the traditional low-level development methods, such as schematic capture or hardware description languages (HDLs), employed to implement these hardware accelerated parts of the design result in a design lifecycle mismatch between the rapid development techniques available for the software programmable parts. This paper presents high-level design languages that enable users to generate netlists for FPGAs directly from high-level C-like languages, thereby offering an equivalent programming solution to that available with microprocessors. It details how one of these languages can be integrated into a high-level design flow for the rapid development of heterogeneous embedded signal-processing systems and presents results from a benchmark.

关键词： hardware engineering FPGA Digital signal processing chips Microprocessors and microcomputers Software engineering techniques digital signal processing chips application specific integrated circuits software engineers high-level C-like languages embedded systems high-level design field-programmable gate arrays low-level development methods hardware acceleration field programmable gate arrays Logic circuits Logic and switching circuits Computer-aided circuit analysis and design high-level design languages Computer-aided logic design ASIC heterogeneous embedded signal-processing systems hardware description languages DSP algorithms High level languages digital signal-processing algorithms design lifecycle Electronic engineering computing application-specific integrated circuit netlists software programmable multiprocessor architecture logic CAD C language embedded signal-processing

来源：评论

学校读者我要写书评

暂无评论

NALLATECH IN-SOCKET FPGA FRONT-SIDE BUS ACCELERATOR

引用

COMPUTING IN SCIENCE & ENGINEERING 2010年第2期12卷 78-82页

作者： Steffen, Craig Genest, Gildas Univ Illinois US Natl Ctr Supercomp Applicat Urbana IL 61801 USA Nallatech Cumbernauld Scotland

field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.

关键词： FPGA front-side bus accelerator field-programmable gate arrays Xeon Xilinx accelerators bandwidth compiler field programmable gate arrays field-programmable gate array low-power electronics reconfigurable socket- based accelerator

来源：评论

学校读者我要写书评

暂无评论

The design of a SRAM-based field-programmable gate array -: Part II:: Circuit design and layout

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1999年第3期7卷 321-330页

作者： Chow, P Seo, SO Rose, J Chung, K Páez-Monzón, G Rahardja, I Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada ATI Technol Thornhill ON L3T 7N6 Canada Xilinx Toronto Dev Ctr Toronto ON M5S 2T9 Canada Natl Semicond Corp Cyrix W Santa Clara CA 95052 USA Aristo Technol Inc Cupertino CA 95104 USA

field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level architectural design of a static random-access memory programmable FPGA, This paper will address the circuit-design issues through to the physical layout. We address area-speed tradeoffs hi the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive, We propose a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort. Thtr minitile is replicated in a 4 x 4 array to create a macro tile. The minitile is optimized for layout density and speed, and is customized in the array by adding appropriate vias, This technique al;so permits easy changing of the hard-wired connections in the logic block architecture and the segmentation length distribution in the routing architecture.

关键词： FPGA FPGA architecture FPGA circuit design field-programmable gate arrays SRAM programmable

来源：评论

学校读者我要写书评

暂无评论

Analysis and architecture design of scalable fractional motion estimation for H.264 encoding

引用

INTEGRATION-THE VLSI JOURNAL 2012年第4期45卷 427-438页

作者： Vasiljevic, Jasmina Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada

Fractional Motion Estimation (FME) is an important part of the H.264/AVC video encoding standard. The algorithm can significantly increase the compression ratio of video encoders while improving video quality. However, it is computationally expensive and can consist of over 45% of the total motion estimation runtime. To maximize the performance and utilization of FME implementations on field-programmable gate arrays (FPGAs), one needs to effectively exploit the inherent parallelism in the algorithm. In this work, we explore two approaches to FME algorithm parallelization in order to effectively increase the processing power of the computing hardware. We call the first method vertical scaling and the second horizontal scaling. We implemented six scaled FME designs on a Xilinx XC5VLX85T (Virtex-5) FPGA. We found that scaling vertically within a 4 x 4 sub-block is more efficient than scaling horizontally across several sub-blocks. As a result, we were able to achieve higher video resolutions at lower hardware resource cost. In particular, it is shown that the best vertically scaled design can achieve 30 fps of QSXGA video with 4 reference frames with only 25.5 K LUTS and 28.7 K registers. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Fractional motion estimation H.264 field-programmable gate arrays Scalability

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：