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From C to netlists: hardware engineering for software engineers?

ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL 2002年第4期14卷 165-173页

作者： Alston, I Madahar, B BAE Syst Ctr Adv Technol Dept Syst Chelmsford CM2 8HN Essex England

The software programmable multiprocessor architecture has been employed extensively over the past two decades for embedded signal-processing applications. However, the increased complexity of such systems has, in many cases, required the use of hardware acceleration to meet the growing time-critical apsects of the design. Today's field-programmable gate arrays (FPGAs) offer an alternative or additional acceleration platform, especially to an application-specific integrated circuit (ASIC). However, the traditional low-level development methods, such as schematic capture or hardware description languages (HDLs), employed to implement these hardware accelerated parts of the design result in a design lifecycle mismatch between the rapid development techniques available for the software programmable parts. This paper presents high-level design languages that enable users to generate netlists for FPGAs directly from high-level C-like languages, thereby offering an equivalent programming solution to that available with microprocessors. It details how one of these languages can be integrated into a high-level design flow for the rapid development of heterogeneous embedded signal-processing systems and presents results from a benchmark.

关键词： hardware engineering FPGA Digital signal processing chips Microprocessors and microcomputers Software engineering techniques digital signal processing chips application specific integrated circuits software engineers high-level C-like languages embedded systems high-level design field-programmable gate arrays low-level development methods hardware acceleration field programmable gate arrays Logic circuits Logic and switching circuits Computer-aided circuit analysis and design high-level design languages Computer-aided logic design ASIC heterogeneous embedded signal-processing systems hardware description languages DSP algorithms High level languages digital signal-processing algorithms design lifecycle Electronic engineering computing application-specific integrated circuit netlists software programmable multiprocessor architecture logic CAD C language embedded signal-processing

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Fast placement approaches for FPGAs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2002年第2期7卷 284-305页

作者： Tessier, R Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

Recent trends in FPGA development indicate a strong shift toward design reuse through the use of intellectual property (IP). This design shift has motivated the development of Frontier, a timing-driven FPGA placement system that uses design macroblocks in conjunction with a series of placement algorithms to achieve highly routable and high-performance layouts quickly. In the first stage of design placement, a macro-based floorplanner is used to quickly identify an initial layout based on intermacro connectivity. Next, FPGA routability and performance metrics are used to evaluate the quality of the initial placement. Finally, if the floorplan is determined to be insufficient from a routability or performance standpoint, a feedback-driven placement perturbation step is employed to achieve a lower cost placement. For a collection of large reconfigurable computing benchmark circuits our timing-driven placement system exhibits a 2.6 x speedup in combined place and route time versus commercial FPGA CAD software with improved design performance for most designs. It is shown that floorplanning, placement evaluation, and backend optimization are all necessary to achieve high-performance placement solutions.

关键词： computer-aided design of VLSI field-programmable gate arrays layout synthesis

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A pipeline of associative memory boards for track finding

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2001年第3期48卷 595-600页

作者： Annovi, A Bagliesi, MG Bardi, A Carosi, R Dell'Orso, M Giannetti, P Iannaccone, G Morsani, F Pietri, M Varotto, G Ist Nazl Fis Nucl Pisa Italy Univ Pisa Dipartimento Fis I-56100 Pisa Italy Univ Pisa Dipartimento Ingn Informaz I-56126 Pisa Italy

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next large hadron collider experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), and increased number of detector layers (by a factor of two). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with a low-cost commercial field-programmable gate array (FPGA). FPGA programming has been optimized for maximum efficiency in terms of pattern density, while printed circuitboard design has been optimized in terms of modularity and FPGA chip density. A complete associative memory board has been successfully tested at 40 MHz;it can contain 7.2 x 10(3) particle trajectories.

关键词： associative memories data acquisition field-programmable gate arrays parallel processing particle tracking pattern matching pattern recognition pipeline processing trigger

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A pipeline of associative memory boards for track finding

A pipeline of associative memory boards for track finding

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Annual Nuclear Science Symposium (NSS)

关键词： associative memories data acquisition field-programmable gate arrays parallel processing particle tracking pattern matching pattern recognition pipeline processing trigger

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A guide to migrating from microprocessor to FPGA coping with the support tool limitations

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MICROPROCESSORS AND MICROSYSTEMS 2000年第10期23卷 561-572页

作者： Bezerra, EA Gough, MP Univ Sussex Ctr Space Sci Sch Engn Brighton BN1 9QT E Sussex England Pontificia Univ Catolica Rio Grande do Sul PUC RS Informat Fac Porto Alegre RS Brazil

Microprocessors have been used as the main processing elements of embedded systems mainly because of their low cost, flexibility for system upgrade at the software level and because of the availability of efficient support tools. The configurable computing technology brought the software flexibility to the hardware level, but limitations in support tools are a barrier for software designers. Using a microcontroller based embedded system as a study case, this paper introduces workable strategies to be used by software designers to develop a complete embedded system (software + hardware parts) using a single description language, and circumventing support tool limitations. (C) 2000 Elsevier Science B.V. All rights reserved.

关键词： configurable computing VHDL field-programmable gate arrays embedded system computer architecture

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Wireless baseband digital signal processing

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2000年第11期35卷 1697-1704页

作者： Zhang, H Prabhu, V George, V Wan, M Benes, M Abnous, A Rabaey, JM Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94704 USA Myricom Inc Arcadia CA 91006 USA

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm x 6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-mum 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network.

关键词： digital signal processors energy conservation field-programmable gate arrays reconfigurable architectures speech coders wireless

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Improved digital tachometer with reduced sensitivity to sensor nonideality

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2000年第4期47卷 890-897页

作者： Kavanagh, RC Natl Univ Ireland Univ Coll Cork Dept Elect & Elect Engn Cork Ireland

A constant sample-time digital tachometer, similar to Ohmae's "M/T" method, is described. This system is capable of accurate determination of shaft velocity, based on the outputs of an incremental encoder. Previous error analyses of such devices which consider only the asynchronous nature of counter operation are shown to be specious. It is highlighted that sensor nonidealities, including variations in the transition locations from their nominal values and phasing errors between encoder channels, can produce much larger tachometer errors. An estimate is made of the actual rms output error, based on a simple encoder model and simplified analysis. It is shown that the error can be significantly reduced by operating four sub-circuits in parallel, each dealing with either a low-to-high or high-to-low transition of a single incremental encoder signal. A field-programmable-gate-array/digital-signal-processor-based practical implementation is described. Both simulation and experimental results are presented which confirm the utility of the enhanced digital tachometer.

关键词： digital measurements field-programmable gate arrays optical transducers optical velocity measurement quantization servo systems tachometers

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Partial-encryption technique for intellectual property protection of FPGA-based products

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2000年第1期46卷 183-190页

作者： Yip, KW Ng, TS Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

The configuration-data sequence of a field-programmable gate array (FPGA) is an intellectual property (IP) of the original designer. This paper proposes a partial-encryption (PE) technique for IP protection of configuration-data sequences by means of increasing the reverse-engineering cost. The PE technique encrypts a few selected data of the sequence. These data are selected in a judicious way such that, when a rival competitor copies the partially encrypted sequence into a cloned product, the cloned product performs the expected task to a certain degree of correctness but not absolutely error-free. Debugging is required. It is shown that, without an initial knowledge that a reverse-engineering countermeasure is employed, the PE technique outperforms the full-encryption technique in terms of the reverse-engineering cost. This paper describes implementation details of the proposed PE technique. Issues regarding system designs that embed hidden imperfections are also discussed.

关键词： partial encryption intellectual property protection reverse engineering reverse-engineering countermeasure field-programmable gate arrays SRAM-based FPGA obfuscation

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The design of a SRAM-based field-programmable gate array -: Part II:: Circuit design and layout

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1999年第3期7卷 321-330页

作者： Chow, P Seo, SO Rose, J Chung, K Páez-Monzón, G Rahardja, I Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada ATI Technol Thornhill ON L3T 7N6 Canada Xilinx Toronto Dev Ctr Toronto ON M5S 2T9 Canada Natl Semicond Corp Cyrix W Santa Clara CA 95052 USA Aristo Technol Inc Cupertino CA 95104 USA

field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level architectural design of a static random-access memory programmable FPGA, This paper will address the circuit-design issues through to the physical layout. We address area-speed tradeoffs hi the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive, We propose a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort. Thtr minitile is replicated in a 4 x 4 array to create a macro tile. The minitile is optimized for layout density and speed, and is customized in the array by adding appropriate vias, This technique al;so permits easy changing of the hard-wired connections in the logic block architecture and the segmentation length distribution in the routing architecture.

关键词： FPGA FPGA architecture FPGA circuit design field-programmable gate arrays SRAM programmable

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The design of an SRAM-based field-programmable gate array -: Part I:: Architecture

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1999年第2期7卷 191-197页

作者： Chow, P Seo, SO Rose, J Chung, K Páez-Monzón, G Rahardja, I ATI Technol Thornhill ON L3T 7N6 Canada Xilinx Toronto Dev Ctr Toronto ON M5S 2T9 Canada Natl Semicond Corp Santa Clara CA 95052 USA Aristo Technol Inc Cupertino CA 95104 USA

field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, acid many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen, and no information on the circuit-level or physical design of the devices. This paper describes the high-level architectural design of a static-random-access memory programmable FPGA. A forthcoming Part II will address the circuit design issues through to the physical layout, The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custom-built computer-aided design tools. The resulting logic block is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.

关键词： field-programmable gate arrays FPGA architecture SRAM programmable

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