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15th International Symposium on Applied Reconfigurable Computing

作者： Liu, Shuanglong Chu, Ringo S. W. Wang, Xiwei Luk, Wayne Imperial Coll London Dept Comp London England UCL Dept Comp Sci London England China Acad Space Technol Beijing Peoples R China

ISBN: (纸本)9783030172268;9783030172275

Hyperspectral image (HSI) classification has been widely adopted in remote sensing imagery analysis applications which require high classification accuracy and real-time processing speed. Convolutional neural networks (CNNs)-based methods have been proven to achieve state-of-the-art accuracy in classifying HSIs. However, CNN models are often too computationally intensive to achieve real-time response due to the high dimensional nature of HSI, compared to traditional methods such as Support Vector Machines (SVMs). Besides, previous CNN models used in HSI are not specially designed for efficient implementation on embedded devices such as FPGAs. This paper proposes a novel CNN-based algorithm for HSI classification which takes into account hardware efficiency and thus is more hardware friendly compared to prior CNN models. An optimized and customized architecture which maps the proposed algorithm on FPGA is then proposed to support real-time on-board classification with low power consumption. Implementation results show that our proposed accelerator on a Xilinx Zynq 706 FPGA board achieves more than 70x faster than an Intel 8-core Xeon CPU and 3x faster than an NVIDIA GeForce 1080 GPU. Compared to previous SVM-based FPGA accelerators, we achieve comparable processing speed but provide a much higher classification accuracy.

关键词： Hyperspectral image classification Deep learning Convolution neural network field-programmable gate array

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Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA 29

Hybrid Dot-Product Calculation for Convolutional Neural Netw...

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29th International Conference on field-programmable Logic and Applications (FPL)

作者： Vestias, Mario Duarte, Rui Policarpo de Sousa, Jose T. Neto, Horacio Inst Politecn Lisboa INESC ID ISEL Lisbon Portugal Univ Lisbon INESC ID Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9781728148847

Convolutional Neural Networks (CNN) are quite useful in edge devices for security, surveillance, and many others. Running CNNs in embedded devices is a design challenge since these models require high computing power and large memory storage. Data quantization is an optimization technique applied to CNN to reduce the computing and memory requirements. The method reduces the number of bits used to represent weights and activations, which consequently reduces the size of operands and of the memory. The method is more effective if hybrid quantization is considered in which data in different layers may have different bit widths. This article proposes a new hardware module to calculate dot-products of CNNs with hybrid quantization. The module improves the implementation of CNNs in low density FPGAs, where the same module runs dot-products of different layers with different data quantizations. We show implementation results in ZYNQ7020 and compare with state-of-the-art works. Improvements in area and performance are achieved with the new proposed module.

关键词： Deep learning Convolutional Neural Network Embedded computing Hybrid quantization field-programmable gate array

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FPGA-based Development of Finite State-MPC for Three-Phase Grid-Connected VSI System 10

FPGA-based Development of Finite State-MPC for Three-Phase G...

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10th International Conference on Power Electronics and ECCE Asia (ICPE - ECCE Asia)

作者： Singh, Vijay Kumar Tripathi, Ravi Nath Hanamoto, Tsuyoshi Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Fukuoka 8080196 Japan Kyushu Inst Technol Next Generat Power Elect Res Ctr Fukuoka 8080196 Japan

ISBN: (纸本)9788957083130

Power converters are used for grid integration of renewable sources that can achieve certain objectives through system control. Finite state - model predictive control (FS-MPC) is one of the techniques used for the grid integration of voltage source inverter (VSI) and possessing distinctive features such as fast dynamic performance and ability to incorporate constraints inherently. However, system development is one of the concern for FS-MPC due to computational delay problem. field programmable gate array (FPGA) based system development is a way to tackle the mentioned problem because of its parallel processing nature. In this paper, FS-MPC is presented for three-phase grid-connected VSI system using modeling-based digital system design approach that is advantageous for analysis, easy debugging and FPGA-based system development. The integrated platform of MATLAB-Simulink and system generator is used for modeling and Hardware-in-the-loop (HIL) simulation to validate the system.

关键词： field-programmable gate array Finite State-MPC Grid-connected VSI Hardware-in-the-loop

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The architecture of a fault-tolerant modular neurocomputer based on modular number projections

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NEUROCOMPUTING 2018年 272卷 96-107页

作者： Chervyakov, N. I. Lyakhov, P. A. Babenko, M. G. Lavrinenko, I. N. Lavrinenko, A. V. Nazarov, A. S. North Caucasus Fed Univ Dept Appl Math & Math Modeling Stavropol Russia North Caucasus Fed Univ Dept Higher Algebra & Geometry Stavropol Russia

This paper suggests a rather efficient architecture for an error correction unit of a residue number system (RNS) that is based on a redundant RNS (RRNS) and applied in parallel data processing structures owing to its capability to improve information stability in calculations. However, the high efficiency of error correction is still not achieved due to the need in the expensive and complex operators that require substantial computational resources and considerable execution time. The suggested error correction method employs the Chinese remainder theorem (CRT) and artificial neural networks (ANN) that appreciably simplify the process of error detection, localization and correction. The key components of the error correction procedure are optimized using (a) the mixed radix conversion (MRC), i.e., the parallel conversion of the numbers from an RNS into the mixed radix number system (MRNS), and (b) the adaptation of neural networks to different sets of RNS moduli (bases) and also to the modular arithmetic during the computation of modular number projections and the restoration of the correct residue on a faulty module. Therefore, the expensive topological structures of neural networks are replaced with the reconfiguration using the weight coefficients switching. In comparison with the existing CRT-based method of projection calculation, the suggested method yields a 20%-30% reduction in power consumption, yet requiring by 10%-20% less FPGA resources for implementation. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Modular neurocomputer Residue number system Fault-tolerance Digital neuron Finite ring neural network field-programmable gate array

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Automated mode recovery for gyrotrons demonstrated at Wendelstein 7-X

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FUSION ENGINEERING AND DESIGN 2019年 148卷 111258-000页

作者： Wilde, F. Marsen, S. Stange, T. Moseev, D. Oosterbeek, J. W. Laqua, H. P. Wolf, R. C. Avramidis, K. Gantenbein, G. Pagonakis, I. Gr Illy, S. Jelonnek, J. Thumm, M. K. Max Planck Inst Plasma Phys Wendelsteinstr 1 DE-17491 Greifswald Mecklenburg Vor Germany KIT IHM D-76131 Karlsruhe Germany KIT IHE D-76131 Karlsruhe Germany

The reliability of gyrotron operation is significantly decreased approaching the individual maximum output power of the tube due to loss of the nominal operating mode. For the first time, this paper proposes an algorithm for an automated mode recovery (MORE) for gyrotrons exploiting the hysteretic gyrotron behaviour. The algorithm has been implemented in a field-programmable gate array (FPGA) controlling the acceleration voltage and is able to recover the nominal operating mode within <1 ms after a mode switch to the competing satellite mode. This allows the gyrotron to be operated closer to its stability limits with extended pulse lengths at potentially higher output power. Dedicated experiments to test MORE were conducted at Wendelstein 7-X (W7-X) with two gyrotrons using a beam dump. The nominal mode could be successfully recovered in 99% of 3755 modeloss events during 128 shots up to 20 s. MORE was operational for nine out of ten gyrotrons during the last experimental campaign OP1.2b of W7-X. The overall success rate during W7-X OP1.2b was 91% counting 464 modeloss events in 131 shots performed with seven gyrotrons. Using the mode losses in the working point plane, the cutoff region for the nominal working mode was identified, defining a minimum cathode current for a given acceleration voltage. The total achievable output power of the W7-X ECRH plant could be increased by at least 500 kW for the same pulse length using MORE, assuming a conservative increase of at least 50 kW per gyrotron. Comparing the output power for the same achievable pulse length and reliability level, the output power increase per gyrotron is likely in the order of 100 kW. Since MORE exploits the hysteretic gyrotron behaviour, it could be applied to other gyrotrons of already existing or future ECRH facilities of fusion experiments, like ITER.

关键词： Gyrotron Mode recovery Satellite mode Hysteretic behaviour field-programmable gate array

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Improvement in Voltage Conversion Ratio of Ultrahigh Step-Down Converter

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ENERGIES 2019年第20期12卷 3896-3896页

作者： Hwu, Kuo-Ing Jiang, Wen-Zhuang Tu, Hsiang-Hao Natl Taipei Univ Technol Dept Elect Engn 1Sec 3Zhongxiao E Rd Taipei 10608 Taiwan Chicony Power Technol Co Ltd New Taipei 21458 Taiwan Delta Elect Inc Taipei 11466 Taiwan

A modified step-down converter is presented herein, which is mainly based on one coupled inductor and several energy-transferring capacitors to improve the voltage conversion ratio as well as to reduce the switch voltage stress. In addition, the portion of the leakage inductance energy can be recycled to the input via the active clamp circuit during the turn-off period and the switches have zero-voltage switching (ZVS) during the turn-on transient. In this paper, the basic operating principles of the proposed converter are firstly described and analyzed, and its effectiveness is finally demonstrated by experiment based on a prototype with input voltage of 60 V, output voltage of 3.3 V and rated output power of 33 W.

关键词： active clamp circuit coupled inductor ultrahigh step-down converter field-programmable gate array zero-voltage switching voltage conversion ratio

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Bit-parallel systolic multiplier over GF(2^m) for irreducible trinomials with ASIC and FPGA implementations

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IET CIRCUITS DEVICES & SYSTEMS 2018年第4期12卷 315-325页

作者： Mathe, Sudha Ellison Boppanal, Lakshmi Natl Inst Technol Dept Elect & Commun Engn Warangal 506004 Telangana India

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre-computation (PC) technique to perform multiplication over for trinomials. Consequently, an m-bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves approximate to 28 and 17% improvement in hardware and area-delay product, respectively, for m=233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area-delay, and power-delay products when compared with similar multipliers available in the literature.

关键词： multiplying circuits application specific integrated circuits field programmable gate arrays cryptography computational complexity bit-parallel systolic multiplier irreducible trinomials ASIC FPGA cryptography cryptographic algorithms finite field multiplications modified interleaved multiplication algorithm computational complexity precomputation technique m-bit systolic multiplier delay complexity analysis SMT structure field-programmable gate array application specific integrated circuit power-delay products

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Hardware implementation and comparison of displacement retrieval algorithms for a laser diode-based optical feedback interferometric sensor

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第4期26卷 1820-1832页

作者： Rehman, Ghazi Zabit, Usman Ullah, Muhammad Obaid Univ Engn & Technol Fac Elect & Elect Engn Dept Elect Engn Taxila Pakistan Natl Univ Sci & Technol Dept Elect Engn Islamabad Pakistan

Optical feedback interferometer (OFI) lasers, also called self-mixing (SM) lasers, have been widely explored over the last couple of decades due to their low cost, compactness, and self-aligned nature and they provide a very good solution for measurements of displacement, vibration, distance, velocity, etc. The SM effect takes place when a part of the laser beam is fed back to the active laser cavity after reflecting from the target. The reflected beam interferes with the emitted beam and hence the optical and spectral characteristics of the laser get changed. To retrieve the vibration or displacement signal of the target from the SM signal, different postprocessing algorithms have been proposed, such as the phase unwrapping method (PUM). The first step of the PUM leads to the coarse estimation of the laser phase and the final step is an iterative joint estimation of 2 parameters, namely laser coupling coefficient C and linewidth enhancement factor alpha. To make this algorithm applicable for real-time measurements, parallel joint estimation for a wide range of C and alpha values needs to be done. In this research, 3 algorithms, namely PUM, direct fringe unwrapping (DFU), and improved DFU (IDFU) were tested for FPGA implementation by using Verilog HDL (hardware description language) so that more precise and real-time vibration and displacement signals of targets could be extracted from the SM sensor in an embedded systems environment. These algorithms were developed using Verilog HDL for implementation on the Xilinx Spartan-3 Xcs400-FG320 development board. Our designed IDFU algorithm performed 0:492 times better than the parallel PUM algorithm in maximum clock frequency and 1:53 and 1:21 times better than the PUM in slice registers and LUT utilization of hardware resources, respectively. The designed DFU algorithm can operate 1:355 times better than IDFU in maximum clock frequency and 25:34 and 14:25 times better than IDFU in slice registers and LUT utilization of

关键词： Self-mixing laser sensors real time phase unwrapping method direct fringe unwrapping improved direct fringe unwrapping field-programmable gate array

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A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography

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IEEE TRANSACTIONS ON COMPUTERS 2018年第11期67卷 1594-1609页

作者： Koziel, Brian Azarderakhsh, Reza Kermani, Mehran Mozaffari Texas Instruments Inc Dallas TX 75243 USA Florida Atlantic Univ Comp & Elect Engn & Comp Sci Dept Boca Raton FL 33431 USA Florida Atlantic Univ I SENSE Boca Raton FL 33431 USA Univ S Florida Comp Sci & Engn Dept Tampa FL 33620 USA

In this work, we present a high-performance and scalable architecture for isogeny-based cryptosystems. In particular, we use the architecture in a fast, constant-time FPGA implementation of the quantum-resistant supersingular isogeny Diffie-Hellman (SIDH) key exchange protocol. On a Virtex-7 FPGA, we show that our architecture is scalable by implementing at 83, 124, 168, and 252-bit quantum security levels. This is the first SIDH implementation at close to the 256-bit quantum security level to appear in literature. Further, our implementation completes the SIDH protocol 2 times faster than performance-optimized software implementations and 1.34 times faster than the previous best FPGA implementation, both running a similar set of formulas. Our implementation employs inversion-free projective isogeny formulas. By replicating multipliers and utilizing an efficient scheduling methodology, we can heavily parallelize quadratic extension field arithmetic and the isogeny evaluation stage of the large-degree isogeny computation. For a constant-time implementation of 124-bit quantum security SIDH on a Virtex-7 FPGA, we generate ephemeral public keys in 8.0 and 8.6 ms and generate the shared secret key in 7.1 and 7.9 ms for Alice and Bob, respectively. Finally, we show that this architecture could also be used to efficiently generate undeniable and digital signatures based on supersingular isogenies.

关键词： Elliptic curve cryptography field-programmable gate array isogeny-based cryptography post quantum cryptography

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A Comparison on Finite-Set Model Predictive Torque Control Schemes for PMSMs

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2018年第10期33卷 8838-8847页

作者： Sandre-Hernandez, Omar Rangel-Magdaleno, Jose Morales-Caporal, Roberto Natl Inst Astrophys Opt & Elect Dept Elect Puebla 72840 Mexico Technol Inst Apizaco Postgrad Studies & Res Div Tlaxcala 90300 Mexico

This paper introduces the comparison of four predictive torque control schemes for a permanent-magnet synchronous machine (PMSM). The first method is the finite-set model predictive control (FS-MPC). In FS-MPC, the optimal switching state is selected based on the evaluation and minimization of a cost function for all possible voltage space vectors (VSVs) of the inverter. The second method performs a simplified FS-MPC where the selection and evaluation of the possible VSVs are reduced to only three. The third method is based on the principle of predictive direct torque control (PDTC), where the duty cycle of the switching state is optimized for application in the inverter. Finally, a method that combines FS-MPC and PDTC named model predictive torque control is presented. This paper introduces the methodology and the results of a comprehensive comparison of the four predictive schemes based on different criterions. The control schemes are implemented on a field-programmable gate array and are applied to a PMSM. Experimental results are presented to validate the presented comparison and discussion.

关键词： field-programmable gate array permanent-magnet synchronous machine (PMSM) predictive control torque control

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