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33rd Great Lakes Symposium on VLSI (GLSVLSI)

作者： Oelund, James Kim, Sunwoong Univ Washington Bothell WA 98011 USA

ISBN: (纸本)9798400701252

Approximate computing provides benefits in the logic area, latency, and/or power without significantly affecting the outputs of some applications. Various approximate computing techniques have been applied for floating-point (FP) dividers that are expensive compared to other FP operators. Since the accuracy requirement varies depending on the application, this paper proposes an accuracy-configurable approximate FP divider design. This design computes the reciprocal of a divisor in a hardware-friendly way. To correct approximation errors, multiple error biases are calculated based on error analysis and stored in a lookup table. The calculated reciprocal is multiplied by a dividend. For accuracy-configurability, an iterative logarithmic FP multiplier is adopted. Compared to previous approximate designs, our proposed design achieves a significantly higher level of accuracy by increasing the number of iterations, at the cost of a slight increase in hardware resources. Compared to the state-of-art Xilinx LogiCORE IP design for accurate FP division, the proposed approximate design reduces the number of lookup table blocks by 53% and the number of flip-flops by 90% in a field-programmable gate array. In JPEG compression, the conventional exact FP multiplier/divider and the proposed design with the number of iterations of 4 show almost the same peak signal-to-noise ratio values.

关键词： approximate computing field-programmable gate arrays floating-point iterative architecture logarithmic divider

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Using FPGA Devices to Accelerate Tree-Based Genetic Programming: A Preliminary Exploration with Recent Technologies 6th

Using FPGA Devices to Accelerate Tree-Based Genetic Programm...

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26th European Conference on Genetic Programming (EuroGP) Held as Part of EvoStar

作者： Crary, Christopher Piard, Wesley Stitt, Greg Bean, Caleb Hicks, Benjamin Univ Florida Gainesville FL 32611 USA

ISBN: (纸本)9783031295720;9783031295737

In this paper, we explore the prospect of accelerating tree-based genetic programming (TGP) by way of modern field-programmable gate array (FPGA) devices, which is motivated by the fact that FPGAs can sometimes leverage larger amounts of data/function parallelism, as well as better energy efficiency, when compared to general-purpose CPU/GPU systems. In our preliminary study, we introduce a fixed-depth, tree-based architecture capable of evaluating type-consistent primitives that can be fully unrolled and pipelined. The current primitive constraints preclude arbitrary control structures, but they allow for entire programs to be evaluated every clock cycle. Using a variety of floating-point primitives and random programs, we compare to the recent TensorGP tool executing on a modern 8nm GPU, and we show that our accelerator implemented on a 14 nm FPGA achieves an average speedup of 43x. When compared to the popular baseline tool DEAP executing across all cores of a 2-socket, 28-core (56-thread), 14nm CPU server, our accelerator achieves an average speedup of 4,902x. Finally, when compared to the recent state-of-the-art tool Operon executing on the same 2-processor CPU system, our accelerator executes about 2.4x slower on average. Despite not achieving an average speedup over every tool tested, our single-FPGA accelerator is the fastest in several instances, and we describe five future extensions that could allow for a 32-144x speedup over our current design as well as allow for larger program depths/sizes. Overall, we estimate that a future version of our accelerator will constitute a state-of-the-art GP system for many applications.

关键词： Tree-based genetic programming field-programmable gate arrays Hardware acceleration

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Secure Lightweight Cryptographic Hardware Constructions for Deeply Embedded Systems

Secure Lightweight Cryptographic Hardware Constructions for ...

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作者： Kaur, Jasmin University of South Florida

学位级别：Ph.D., Doctor of Philosophy

Lightweight cryptography plays a vital role in securing resource-constrained deeply embedded systems such as implantable and wearable medical devices, smart fabrics, smart homes, radio frequency identification tags, sensor networks, and privacy-constrained usage models. The National Institute of Standards and Technology (NIST) initiated a standardization process for lightweight cryptography, a relatively-long multi-year effort, which eventually concluded in February 2023. Side-channel attacks (SCAs) exploit the vulnerabilities of a system by observing and analyzing side-channel information leakages. Fault analysis attacks are a type of active SCAs, where an intelligent adversary injects bit/byte faults into the implementation of a cryptographic cipher to recover the secret key. This dissertation tackles active fault attacks by applying different error detection strategies as countermeasures to the crucial components of different state-of-the-art lightweight cryptosystems in their hardware applications. The case studies include lightweight cryptographic ciphers - QARMA, Welch-Gong ciphers WAGE and WG-29, and ASCON, the winner of the NIST standardization process for lightweight cryptography in February 2023. The proposed error detection schemes are designed to be architecture-oblivious as well as low-cost in hardware constructions of the ciphers listed above. The schemes are benchmarked on the field-programmable gate array (FPGA) hardware platform for error coverage and performance evaluation via implementation overheads. The results of the proposed works in this dissertation lead to more reliable lightweight cryptography, immune against fault analysis attacks.

关键词： Differential fault analysis Error detection field-programmable gate arrays Lightweight cryptography Side-channel attacks

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Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

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IEEE ACCESS 2021年 9卷 115599-115619页

作者： Seifoori, Zeinab Asadi, Hossein Stojilovic, Mirjana Sharif Univ Technol Dept Comp Engn Tehran *** Iran Ecole Polytech Fed Lausanne EPFL Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA routing resources. In the first group of proposed algorithms, we employ K-means clustering and exploit the utilization pattern of routing resources. In the second group of algorithms, we enhance the power-gating efficiency by minimizing the power overhead introduced by power-gating logic and by taking into account the size of routing multiplexers, which influences the power-gating efficiency. Finally, we enhance and further develop the baseline FPGA routing algorithm to be aware and take advantage of power gating opportunities. The experimental results on Titan benchmark suite and the latest Intel Stratix-IV FPGA architecture in VTR 8.0 show that our approaches achieve an improvement of about 70%, on average, in reducing the FPGA static power consumption over the best power-gating approaches proposed in the previous studies.

关键词： field programmable gate arrays Routing Power demand Clustering algorithms Machine learning algorithms Switches Benchmark testing field-programmable gate arrays static power consumption power gating routing algorithm machine learning

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FPGA-based hardware implementation of chaotic opposition-based arithmetic optimization algorithm

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APPLIED SOFT COMPUTING 2024年 154卷

作者： Zermani, Mohamed Aymen Manita, Ghaith Chhabra, Amit Feki, Elyes Mami, Abdelkader Tunis El Manar Univ Dept Phys LAPER Fac Sci Campus Univ El Manar Tunis 2092 Tunisia Univ Manouba ESEN Manouba Tunisia Univ Sousse Lab MARS ISITCom LR17ES05 Sousse Tunisia Guru Nanak Dev Univ Dept Comp Engn & Technol Amritsar India

The hardware implementation of optimization algorithms has gained significant attention due to its potential for augmenting performance and efficiency. This paper presents the hardware implementation of a Chaotic Opposition-Based Arithmetic Optimization Algorithm (COAOA). COAOA is inspired by integrating chaotic dynamics and opposition-based learning (OBL) principles in the original AOA algorithm. Inspired by chaotic maps, COAOA amplifies exploration and exploitation capabilities, while OBL enhances the search process by considering both positive and negative solution counterparts. Our proposed hardware implementation of COAOA harnesses field-programmable gate arrays (FPGAs) to accelerate optimization processes. Leveraging FPGA's parallel processing capabilities, the COAOA algorithm is efficiently parallelized and mapped onto the hardware architecture, streamlining arithmetic operations and governing algorithmic execution flow. To assess its efficacy, a comparison was made between the performance of the suggested structure and five alternative algorithms: opposition-based learning AOA (OAOA), Chaotic AOA, the original AOA, PSO and GA. Statistical analyses and tests were performed using benchmark functions like Rosenbrock, Rastrigin, Six-Hump CamelBack, and Zirilli functions. The empirical findings indicate the substantial acceleration achieved through the hardware implementation of COAOA compared to the original AOA algorithm and its variants. This compelling outcome positions COAOA as a viable solution for real-time optimization challenges, signifying its potential to significantly expedite optimization tasks in practical applications.

关键词： Arithmetic optimization algorithm Chaotic random Opposition -based method field-programmable gate arrays Hardware implementation

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A Reconfigurable Framework for Hybrid Quantum-Classical Computing

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ALGORITHMS 2025年第5期18卷 271-271页

作者： Pratibha, Naveed Mahmud, Naveed Florida Inst Technol Coll Engn & Sci Dept Elect Engn & Comp Sci 150 W Univ Blvd Melbourne FL 32901 USA

Hybrid quantum-classical (HQC) computing refers to the approach of executing algorithms coherently on both quantum and classical resources. This approach makes the best use of current or near-term quantum computers by sharing the workload with classical high-performance computing. However, HQC algorithms often require a back-and-forth exchange of data between quantum and classical processors, causing system bottlenecks and leading to high latency in applications. The objective of this study is to investigate novel frameworks that unify quantum and reconfigurable resources for HQC and mitigate system bottleneck and latency issues. In this paper, we propose a reconfigurable framework for hybrid quantum-classical computing. The proposed framework integrates field-programmable gate arrays (FPGAs) with quantum processing units (QPUs) for deploying HQC algorithms. The classical subroutines of the algorithms are accelerated on FPGA fabric using a high-throughput processing pipeline, while quantum subroutines are executed on the QPUs. High-level software is used to seamlessly facilitate data exchange between classical and quantum workloads through high-performance channels. To evaluate the proposed framework, an HQC algorithm, namely variational quantum classification, and the MNIST dataset are used as a test case. We present a quantitative comparison of the proposed framework with a state-of-the-art quantum software framework running on a server-grade CPU. The results demonstrate that the FPGA pipeline achieves up to 8x improvement in runtime compared to the CPU baseline.

关键词： hybrid quantum-classical computing reconfigurable computing field-programmable gate arrays

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Virtualizing Reconfigurable Architectures: From FPGAs to Beyond

Virtualizing Reconfigurable Architectures: From FPGAs to Bey...

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作者： Zha, Yue University of Pennsylvania

学位级别：Ph.D., Doctor of Philosophy

With field-programmable gate arrays (FPGAs) being widely deployed in data centers to enhance the computing performance, an efficient virtualization support is required to fully unleash the potential of cloud FPGAs. However, the system support for FPGAs in the context of the cloud environment is still in its infancy, which leads to a low resource utilization due to the tight coupling between compilation and resource allocation. Moreover, the system support proposed in existing works is limited to a homogeneous FPGA cluster comprising identical FPGA devices, which is hard to be extended to a heterogeneous FPGA cluster that comprises multiple types of FPGAs. As the FPGA cloud is expected to become increasingly heterogeneous due to the hardware rolling upgrade strategy, it is necessary to provide efficient virtualization support for the heterogeneous FPGA cluster. In this dissertation, we first identify three pairs of conflicting requirements from runtime management and offline compilation, which are related to the tradeoff between flexibility and efficiency. These conflicting requirements are the fundamental reason why the single-level abstraction proposed in prior works for the homogeneous FPGA cluster cannot be trivially extended to the heterogeneous cluster. To decouple these conflicting requirements, we provide a two-level system abstraction. Specifically, the high-level abstraction is FPGA-agnostic and provides a simple and homogeneous view of the FPGA resources to simplify the runtime management and maximize the flexibility. On the contrary, the low-level abstraction is FPGA-specific and exposes sufficient low-level hardware details to the compilation framework to ensure the mapping quality and maximize the efficiency. This generic two-level system abstraction can also be specialized to the homogeneous FPGA cluster and/or be extended to leverage application-specific information to further improve the efficiency. We also develop a compilation framework and a modul

关键词： Cloud computing field-programmable gate arrays Virtualization

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Boosting Domain-Specific Debug Through Inter-frame Compression 21

Boosting Domain-Specific Debug Through Inter-frame Compressi...

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21st International Conference on field-programmable Technology (ICFPT)

作者： Nafziger, Zakary Chua, Martin Noronha, Daniel Holanda Wilton, Steven J. E. Univ British Columbia Vancouver BC Canada

ISBN: (数字)9781665453363

ISBN: (纸本)9781665453363

Acceleration of machine learning models is proving to be an important application for FPGAs. Unfortunately, debugging such models during training or inference is difficult. Software simulations of a machine learning system may be of insufficient detail to provide meaningful debug insight, or may require infeasibly long run-times. Thus, it is often desirable to debug the accelerated model while it is running on real hardware. Effective on-chip debug often requires instrumenting a design with additional circuitry to store run-time data, consuming valuable chip resources. Previous work has developed methods to perform lossy compression of signals by exploiting machine learning specific knowledge, thereby increasing the amount of debug context that can be stored in an on-chip trace buffer. However, all prior work compresses each successive element in a signal of interest independently. Since debug signals may have temporal similarity in many machine learning applications there is an opportunity to further increase trace buffer utilization. In this paper, we present an architecture to perform lossless temporal compression in addition to the existing lossy elementwise compression. We show that, when applied to a typical machine learning algorithm in realistic debug scenarios, we are able to store twice as much information in an on-chip buffer while increasing the total area of the debug instrument by approximately 25%. The impact is that, for a given instrumentation budget, a significantly larger trace window is available during debug, possibly allowing a designer to narrow down the root cause of a bug faster.

关键词： field-programmable gate arrays Debug Instrumentation

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A novel Laplacian vector directional filter designed for real-time removal of impulsive noise from color images

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COMPUTERS & ELECTRICAL ENGINEERING 2024年第PartA期118卷

作者： Ben Atitallah, Ahmed Alanazi, Meshari D. Jouf Univ Coll Engn Dept Elect Engn Sakaka Saudi Arabia

Eliminating noise from a color image represents an essential task in image processing, given that noise can markedly diminish visual quality and impact the precision of subsequent analyses or applications (such as visual quality inspection, medical image analysis, etc.). In this study, we introduce an innovative approach designed to remove noise while preserving the edges and fine details of a color image. This method is based on Laplacian operators, threshold values for identifying potentially corrupted pixels due to noise, and the Vector Directional Filter (VDF) for substituting noisy pixels. Consequently, this technique is termed Laplacian VDF (LVDF). Additionally, a Hardware/Software (HW/SW) design is formulated for the real-time implementation of the LVDF filter. The hardware architecture is designed through the High-Level Synthesis (HLS) flow, while the software component is executed using the ARM Cortex-A53 hardcore processor. Furthermore, five Direct Memory Access (DMAs) are employed to enhance data throughput between the hardware coprocessor and Double Data Rate (DDR) memory. Performance evaluations conducted on the ZCU102 kit reveal that the LVDF HW/SW design facilitates the restoration of 74 images per second, resulting in a 94 % reduction in execution time compared to the software implementation, all while maintaining consistent objective and subjective image quality.

关键词： Nonlinear filter Real-time image denoising Hardware/Software codesign High-level synthesis flow field-programmable gate arrays Computational optimization

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Improved Direct Current Control for Grid-Connected Multilevel Inverters

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2021年第9期68卷 8289-8297页

作者： Hofmann, Martin Schaefer, Markus Montesinos-Miracle, Daniel Ackva, Ansgar Univ Appl Sci Wuerzburg Schweinfurt Elect Engn Dept D-97421 Schweinfurt Germany ZF Friedrichshafen AG E Mobil D-97424 Schweinfurt Germany Univ Politecn Cataluna Ctr Innovacio Tecnol Convertidors Estat & Acciona Dept Engn Elect Barcelona 08034 Spain

This article presents a sensorless voltage detection method for direct current control in grid-connected multilevel inverters. The direct current control is based on scalar hysteresis controller (SHC). The SHC is a simplified, and parametric direct current controller with the ability to work with an arbitrary level count on multilevel inverters. In combination with the sensorless voltage detection method, it is able to improve the switching behavior, and minimize the current error compared to existing direct current controllers. The proposed control concept is validated with experimental measurements using a three-, and five-level diode clamped inverter under steady-state conditions, and various grid disturbances. In comparison to the standard SHC method, it is verified that the proposed concept shows an improved switching behavior, and a reduced error current.

关键词： Inverters Switches Voltage control Current control Aerospace electronics Hysteresis Current control field-programmable gate arrays multilevel systems robust control

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