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ENGINEERING REPORTS 2025年第1期7卷

作者： Deng, Quan Liu, Qiang Tianjin Univ Sch Microelect Tianjin Peoples R China Tianjin Key Lab Imaging & Sensing Microelect Techn Tianjin Peoples R China

Molecular dynamics simulation is a common method to help humans understand the microscopic world. The traditional general-purpose high-performance computing platforms are hindered by low computational and power efficiency, constraining the practical application of large-scale and long-time many-body molecular dynamics simulations. In order to address these problems, a novel molecular dynamics accelerator for the Tersoff potential is designed based on field-programmable gate array (FPGA) platforms, which enables the acceleration of LAMMPS using FPGAs. Firstly, an on-the-fly method is proposed to build neighbor lists and reduce storage usage. Besides, multilevel parallelizations are implemented to enable the accelerator to be flexibly deployed on FPGAs of different scales and achieve good performance. Finally, mathematical models of the accelerator are built, and a method for using the models to determine the optimal-performance parameters is proposed. Experimental results show that, when tested on the Xilinx Alveo U200, the proposed accelerator achieves a performance of 9.51 ns/day for the Tersoff simulation in a 55,296-atom system, which is a 2.00x$$ \times $$ increase in performance when compared to Intel I7-8700K and 1.70x$$ \times $$ to NVIDIA Tesla K40c under the same test case. In addition, in terms of computational efficiency and power efficiency, the proposed accelerator achieves improvements of 2.00x$$ \times $$ and 7.19x$$ \times $$ compared to Intel I7-8700K, and 4.33x$$ \times $$ and 2.11x$$ \times $$ compared to NVIDIA Titan Xp, respectively.

关键词： field-programmable gate array high-performance computing molecular dynamics reconfigurable computing Tersoff potential

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Parallelized field-programmable gate array Data Processing for High-Throughput Pulsed-Radar Systems

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SENSORS 2025年第1期25卷 239页

作者： Pitcher, Aaron D. Georgiev, Mihail Nikolova, Natalia K. Nicolici, Nicola McMaster Univ Electromagnet Vis EMVi Res Lab Hamilton ON L8S 4L8 Canada McMaster Univ Comp Aided Design & Test CADT Res Grp Hamilton ON L8S 4L8 Canada

A parallelized field-programmable gate array (FPGA) architecture is proposed to realize an ultra-fast, compact, and low-cost dual-channel ultra-wideband (UWB) pulsed-radar system. This approach resolves the main shortcoming of current FPGA-based radars, namely their low processing throughput, which leads to a significant loss of data provided by the radar receiver. The architecture is integrated with an in-house UWB pulsed radar operating at a sampling rate of 20 gigasamples per second (GSa/s). It is demonstrated that the FPGA data-processing speed matches that of the radar output, thus eliminating data loss. The radar system achieves a remarkable speed of over 9000 waveforms per second on each channel. The proposed architecture is scalable to accommodate higher sampling rates and various waveform periods. It is also multi-functional since the FPGA controls and synchronizes two transmitters and a dual-channel receiver, performs signal reconstruction on both channels simultaneously, and carries out user-defined averaging, trace windowing, and interference suppression for improving the receiver's signal-to-noise ratio. We also investigate the throughput rate while offloading radar data onto an external device through an Ethernet link. Since the radar data rate significantly exceeds the Ethernet link capacity, we show how the FPGA-based averaging and windowing functions are leveraged to reduce the amount of offloaded data while fully utilizing the radar output.

关键词： concealed weapon detection field-programmable gate array equivalent-time sampling subsampling ultra-wideband measurement techniques ultra-wideband radar

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field-programmable gate array Based Fuzzy Sliding-mode Controller for a Permanent Magnet Synchronous Motor Drive

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ELECTRIC POWER COMPONENTS AND SYSTEMS 2014年第13期42卷 1440-1451页

作者： Zhan, Lixin Zhou, Kai Tsinghua Univ Dept Mech Engn Beijing 100084 Peoples R China

In this article, a field-programmable gate array based fuzzy sliding-mode controller is proposed to control a permanent magnet synchronous motor drive. First, the dynamics of a permanent magnet synchronous motor is derived, and the vector control scheme is introduced in the current loop. Next, to improve the performance of the permanent magnet synchronous motor drive, a fuzzy sliding-mode controller with an integral-operation switching surface is proposed and applied to the speed loop, in which a fuzzy inference mechanism is adopted to generate the reaching control signal. Further, an integrated hardware design method is developed to implement the field-oriented vector current controller and the proposed fuzzy sliding-mode speed controller on a single field programmable gate array chip. Finally, a prototyping platform based on an Altera field-programmable gate array is established to evaluate the ability of the proposed fully integrated solution in terms of control quality and time/area performances. The preferable performance of the proposed field-programmable gate array-based fuzzy sliding-mode control approach for permanent magnet synchronous motor drive is verified by the experimental results compared with the conventional proportional-integral control and sliding mode control schemes.

关键词： field-programmable gate array permanent magnet synchronous motor fuzzy inference mechanism sliding-mode control fuzzy sliding-mode control control integrated circuit field-oriented vector control speed controller permanent magnet synchronous motor drive integrated hardware design

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field-programmable gate array-based intelligent dynamic sliding-mode control using recurrent wavelet neural network for linear ultrasonic motor

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IET CONTROL THEORY AND APPLICATIONS 2010年第9期4卷 1511-1532页

作者： Lin, F. -J. Hung, Y. -C. Chen, S. -Y. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan

A field-programmable gate array (FPGA)-based intelligent dynamic sliding-mode control (IDSMC) using recurrent wavelet neural network (RWNN) estimator is proposed to control the mover position of a linear ultrasonic motor (LUSM) in this study. First, the structure and operating principles of the LUSM are introduced briefly. Then, the dynamics of LUSM mechanism with the introduction of a lumped uncertainty, which include the friction force, is derived. Since the dynamic characteristics and motor parameters of the LUSM are non-linear and time-varying, an IDSMC using RWNN estimator is designed to achieve robust control performance of the LUSM drive system. The RWNN estimator is employed to estimate the non-linear functions including the system parameters and external disturbance. Moreover, the adaptive learning algorithm trained the parameters of the RWNN online is derived using the Lyapunov stability theorem. Furthermore, an FPGA chip is adopted to implement the developed control and on-line learning algorithms for possible low-cost and high-performance industrial applications. The experimental results show that excellent positioning and tracking performance are achieved. In addition, the robustness to parameter variations and friction force can be obtained as well using the proposed control system.

关键词： linear motors friction force adaptive control Control of electric power systems intelligent dynamic sliding-mode control lumped uncertainty recurrent neural nets Multivariable control systems ultrasonic motors neurocontrollers Logic and switching circuits variable structure systems Stability in control theory control system synthesis Linear machines Control system analysis and synthesis methods control engineering electric machine analysis computing Logic circuits recurrent wavelet neural network robust control field programmable gate arrays Self-adjusting control systems Lyapunov methods Control engineering computing machine control Neurocontrol uncertain systems Piezoelectric motors field-programmable gate array adaptive learning algorithm Power engineering computing linear ultrasonic motor Lyapunov stability theorem

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field-programmable gate array-based functional link radial basis function network control for permanent magnet linear synchronous motor servo drive system

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IET ELECTRIC POWER APPLICATIONS 2010年第5期4卷 357-372页

作者： Lin, F. -J. Chou, P. -H. Hung, Y. -C. Wang, W. -M. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan Natl Dong Hwa Univ Dept Elect Engn Hualien 974 Taiwan

A field-programmable gate array (FPGA)-based functional link radial basis function network (FLRBFN) control is proposed in this study to control the mover of a permanent magnet linear synchronous motor (PMLSM) servo drive system to track periodic reference trajectories. First, the dynamics of the field-oriented control PMLSM servo drive with a lumped uncertainty, which contains parameter variations, external disturbances and non-linear friction force, is derived. Then, to achieve accurate trajectory tracking performance with robustness, an intelligent control approach using FLRBFN is proposed for the field-oriented control PMLSM servo drive system. The proposed FLRBFN is a radial basis function network (RBFN) embedded with a functional link neural network (FLNN). Moreover, the on-line learning algorithm of the FLRBFN, including the connective weights, the centres and the centres' width of the receptive field functions, are derived using back-propagation (BP) method. Furthermore, an FPGA chip is adopted to implement the developed control and on-line learning algorithms for possible low-cost and high-performance industrial applications using PMLSM. Finally, the effectiveness of the proposed control scheme and the robustness to parameter variations, external disturbances and friction force of the PMLSM servo drive system are verified by some experimental results.

关键词： field-oriented control linear motors machine vector control Control of electric power systems backpropagation method lumped uncertainty FPGA neurocontrollers permanent magnet linear synchronous motor servo drive system synchronous motor drives Linear machines Actuating and final control devices trajectory tracking performance RBFN functional link radial basis function network control field programmable gate arrays servomechanisms permanent magnet motors Synchronous machines Neurocontrol field-programmable gate array backpropagation radial basis function networks nonlinear friction force intelligent control approach Drives

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field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2021年第4期29卷 2127-2139页

作者： Kashif, Muhammad Cicek, Ihsan Istanbul Sehir Univ Dept Elect Engn Istanbul Turkey Istinye Univ Dept Elect Engn Istanbul Turkey

Elliptic curve cryptography provides a widely recognized secure environment for information exchange in resource-constrained embedded system applications, such as Internet-of-Things, wireless sensor networks, and radio frequency identification. As the elliptic-curve cryptography (ECC) arithmetic is computationally very complex, there is a need for dedicated hardware for efficient computation of the ECC algorithm in which scalar point multiplication is the performance bottleneck. In this work, we present an ECC accelerator that computes the scalar point multiplication for the NIST recommended elliptic curves over Galois binary fields by using a polynomial basis. We used the Montgomery algorithm with projective coordinates for the scalar point multiplication. We designed a hybrid finite field multiplier based on the standard Karatsuba and shift-and-add multiplication algorithms that achieve one finite field multiplication in m2 clock cycles for a key-length of m. The proposed design has been modeled in Verilog hardware description language (HDL), functionally verified with simulations, and implemented for field-programmable gate array (FPGA) devices using vendor tools to demonstrate hardware efficiency. Finally, we have integrated the ECC accelerator as an AXI4 peripheral with a synthesizable microprocessor on an FPGA device to create an elliptic curve crypto-processor.

关键词： Elliptic curve cryptography Karatsuba multiplier crypto-accelerator crypto-processor scalar multiplica-tion field-programmable gate array

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field-programmable gate array-Based Coating Impedance Detector for Rapid Evaluation of Early Degradation of Protective Coatings

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IEEE ACCESS 2019年 7卷 20472-20478页

作者： Lee, Yueh-Lien Kuo, Yu-Tong Chen, Hung-Hsun Hsieh, Yung-An Natl Taiwan Univ Dept Engn Sci & Ocean Engn Taipei 10617 Taiwan

In this paper, a novel, compact, And field-programmable gate array (FPGA)-based coating impedance detector (CID 2.0) was proposed to rapidly detect the early degradation of coatings. An FPGA-based hardware design with an embedded analog-to-digital converter and digital-to-analog converter was successfully applied to develop CID 2.0. A method for generating high-quality signals for FPGA by using the delta-sigma modulation was used. This method provided higher measurement ranges and accuracies for detecting coating impedance values. The performance of CID 2.0 was compared with that of a conventional potentiostat. For comparison, the impedance value of ideal resistors and commercial coatings was measured using the proposed and conventional methods. The results indicated an optimal correlation between the impedance values measured using CID 2.0 and that measured using conventional potentiostat in the range of 10(6) - 10(10) Omega-cm(2). Furthermore, when the continuous monitoring experiments were conducted, CID 2.0 exhibited high sensitivity to detect impedance changes associated with the coating delamination process. The preliminary results suggested that CID 2.0 can be used to observe the changes in the coating impedance values in the critical range to enable workers to determine whether coating maintenance should be scheduled.

关键词： Coating corrosion monitor electrochemical impedance spectroscopy impedance measurement field-programmable gate array

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field-programmable gate array implementation of a single photoncounting receive modem 36

Field-programmable gate array implementation of a single pho...

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Conference on Free-Space Laser Communications XXXVI

作者： Simon, William P. Downey, Jennifer N. Lantz, Nicholas C. Bizon, Thomas P. Marsden, Michael A. Vyhnalek, Brian E. Zeleznikar, Daniel J. NASA Glenn Res Ctr 21000 Brookpk Rd Cleveland OH 44135 USA

ISBN: (纸本)9781510670150;9781510670143

We present a field-programmable gate array (FPGA) implementation of a single photon-counting receive modem for a pulse position modulated signal. The modem is compliant with the Consultative Committee for Space Data Systems (CCSDS) High Photon Efficiency (HPE) Optical Communications Coding and Synchronization standard and is capable of a maximum data rate of 267 Mbps. The system is designed on a commercial off-the-shelf FPGA platform and utilizes superconducting nanowire single photon counting detectors, analog to digital converters (ADCs) to sample the detectors, and two FPGAs. Symbol timing recovery, photon counting, convolutional deinterleaving, and codeword synchronization are performed in the first FPGA. The second FPGA performs iterative decoding on each codeword of the serially concatenated pulse position modulated (SCPPM) signal. A digital filter is included to compensate for timing jitter of the detector, and the decoder throughput can be adjusted through reconfigurable parallelization. The decoder also implements a resource-efficient, algorithmic polynomial interleaver and deinterleaver. Both FPGAs can be reconfigured to switch between pulse position modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver architecture and FPGA implementation of the timing recovery loop and SCPPM decoder, FPGA utilization for the different modes, and receive modem characterization test results.

关键词： field-programmable gate array optical receiver timing recovery iterative decoder

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Hardware implementation and performance analysis of MPTD-CSMA protocol based on field-programmable gate array in VANET

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IET COMMUNICATIONS 2020年第16期14卷 2769-2779页

作者： Ding, Hongwei Lu, Xu Li, Bo Wang, Liqing Bao, Liyong Yang, Zhijun Liu, Qianlin Yunnan Univ Sch Informat Kunming 650091 Yunnan Peoples R China

Contention-based carrier sense multiple access (CSMA) and contention-free time division multiple access (TDMA) protocol are two typical access protocols of media access control in vehicularad hocnetwork (VANET). They all show their unique advantages under specific conditions. TDMA has high transmission reliability, CSMA has a low transmission delay in the communication environment with low packet arrival rate. However, when the arrival rate of information packets increases rapidly, the throughput of CSMA will decrease rapidly and approach zero, which is not suitable for data transmission in the communication environment with a high arrival rate of information packets;while data transmission through a single TDMA protocol will cause high system overhead due to strict synchronous information. Aiming at the defects of the two protocols and the multi-channel communication environment, this study proposes the optimised protocol model multi-priority time division-CSMA (MPTD-CSMA). The optimised protocol model not only ensures the reliability of data communication but also reduces the transmission delay of the system. At the same time, the multi-priority mechanism is added to increase the channel utilisation of the protocol model.

关键词： protocols mobile radio vehicular ad hoc networks wireless channels data communication field programmable gate arrays carrier sense multiple access time division multiple access access protocols ad hoc networks VANET high transmission reliability low transmission delay low packet arrival rate information packets data transmission high arrival rate single TDMA protocol high system strict synchronous information multichannel communication environment optimised protocol model multipriority time division-CSMA data communication performance analysis MPTD-CSMA protocol field-programmable gate array contention-free time division typical access protocols media access control vehicular ad hoc network

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Embedded linear model predictive control in field-programmable gate array using register-transfer level implementation and floating-point representation applied to a quadrotor system model

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2022年第2期236卷 370-381页

作者： Castanheira de Farias, Alceu Bernardes Murilo, Andre Lopes, Renato Vilela Univ Brasilia Fac Technol Dept Mech Engn Campus Univ Darcy Ribeiro BR-70910900 Brasilia DF Brazil Univ Brasilia Fac Gama Area Especial Ind Projecao A Setor Leste Brasilia DF Brazil

Model predictive control is increasingly becoming a popular control strategy for a wide range of applications in both industry and academia, mainly motivated by its ability to systematically handle constraints imposed on a system, regardless of its nature. However, this generates high computational demands, limiting the applicability of model predictive control. field-programmable gate arrays are reconfigurable hardware platforms that allow the parallel implementation of model predictive control, accelerating such algorithms, but most works found in the literature opt to use high-level synthesis tools and fixed-point numeric representation to generate embedded controllers, resulting in faster-designed solutions but not exactly efficient and flexible ones, that can be applied to different scenarios. Regarding such matter, this work proposes the manual implementation (register-transfer level implementation) of linear model predictive control and the usage of floating-point numeric representation applied to a quadrotor system. The initial results obtained using the proposed controller are presented in this article, achieving 29.34 ms of calculation time at 50 MHz for the attitude control of a quadrotor model containing twelve states and four control outputs.

关键词： Control systems embedded systems model predictive control field-programmable gate array quadrotor

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