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FPGA-Based Hardware Design for Scale-Invariant Feature Transform

IEEE ACCESS 2018年 6卷 43850-43864页

作者： Li, Shih-An Wang, Wei-Yen Pan, Wei-Zheng Hsu, Chen-Chien James Lu, Cheng-Kai Tamkang Univ Dept Elect Engn New Taipei 25137 Taiwan Natl Taiwan Normal Univ Dept Elect Engn Taipei 10610 Taiwan Univ Teknol PETRONAS Dept Elect & Elect Engn Bandar Seri Iskandar 32610 Malaysia

This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.

关键词： Scale-invariant feature transform field-programmable gate array parallel processing architecture

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A fast method for particle tracking and triggering using small-radius silicon detectors

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2020年第0期957卷 163427-000页

作者： Kotwal, Ashutosh V. Duke Univ Dept Phys Durham NC 27708 USA

We propose an algorithm, deployable on a highly-parallelized graph computing architecture, to perform rapid reconstruction of charged-particle trajectories in the high energy collisions at the Large Hadron Collider and future colliders. We use software emulation to show that the algorithm can achieve an efficiency in excess of 99.95% for reconstruction with good accuracy. The algorithm can be implemented on silicon-based integrated circuits using field-programmable gate array technology. Our approach can enable a fast trigger for massive charged particles that decay invisibly in the tracking volume, as in some new-physics scenarios related to particulate dark matter. If production of dark matter or other new neutral particles is mediated by metastable charged particles and is not associated with other triggerable energy deposition in the detectors, our method would be useful for triggering on the charged mediators using the small-radius silicon detectors.

关键词： Charged particle tracking Track trigger Unsupervised machine learning field-programmable gate array Electronics

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Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第2期26卷 919-935页

作者： Ayat, Sayed Omid Khalil-Hani, Mohamed Ab Rahman, Ab Al-Hadi Univ Teknol Malaysia Fac Elect Engn VeCAD Res Lab Skudai Johor Malaysia

In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

关键词： Convolutional neural network field-programmable gate array energy efficiency Roofline model race-to-halt strategy

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An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2016年第5期E99D卷 1285-1295页

作者： Liu, Leibo Wang, Dong Chen, Yingjie Zhu, Min Yin, Shouyi Wei, Shaojun Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Beijing Jiaotong Univ Inst Informat Sci Beijing Peoples R China

This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 x 16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6x performance gain over an industrial coarse-grained reconfigurable processor for H. 264 decoding, and a 6.43x performance boosts over a general purpose processor based implementation for HEVC decoding.

关键词： algorithm mapping coarse-grained reconfigurable array field-programmable gate array reconfigurable computing video decoding

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Development of Compact, Cost-effective, FPGA-Based Data Acquisition System for the iPET System

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JOURNAL OF MEDICAL AND BIOLOGICAL ENGINEERING 2017年第6期37卷 858-866页

作者： Min, Eungi Kim, Kwangdon Lee, Hakjae Kim, Hyun-Il Chung, Yong Hyun Kim, Yongkwon Joung, Jinhun Kim, Kyeong Min Joo, Sung-Kwan Lee, Kisung Korea Univ Dept IT Convergence Seoul South Korea Korea Univ Dept Bioconvergence Engn Seoul South Korea Korea Univ Sch Biomed Engn Seoul South Korea Yonsei Univ Dept Radiat Convergence Engn Wonju South Korea Korea Inst Nucl Safety Daejeon South Korea NuCare Inc Incheon South Korea Korea Inst Radiol & Med Sci Div Med Radiat Equipment Seoul South Korea Korea Univ Sch Elect Engn Seoul South Korea

Positron emission tomography (PET) is a nuclear medicine imaging technology used to analyze physiological processes. An in-beam PET is used to verify the delivered dose during ion-beam therapy. Our group investigates the prototype C-shaped PET system, which is called the iPET system. In this study, we develop an expendability-enhanced field-programmable gate array (FPGA)-based data acquisition system for the iPET. We organize this data acquisition (DAQ) system using only one DAQ board, to ensure a compact and cost-effective DAQ system. We design the FPGA using modular functions, which include synchronization, deserialization, pulse height analysis, and data packaging functions. As a result, energy spectra and well-separated 9 x 9 flood images of the entire detector module are achieved. We obtain reconstructed PET images of point source (4 mm diameter), three cylindrical phantoms (3 cm diameter), and four sphere phantoms (3.0, 2.2, 1.3 and 1.0 cm diameter). We achieve approximately 300 kcps of maximum single count rate. The obtained results prove the compactness and cost-effectiveness of the proposed DAQ system.

关键词： In-beam PET Data acquisition system field-programmable gate array Modular function

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Simple and robust self-healing technique for millimetre-wave amplifiers

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IET CIRCUITS DEVICES & SYSTEMS 2016年第1期10卷 37-43页

作者： Jia, Haikun Chi, Baoyong Kuang, Lixue Wang, Zhihua Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

A simple and robust self-healing technique for millimetre-wave (mm-wave) amplifiers is proposed. The self-healing technique can correct the operation frequency shifting of the amplifier (including its input and output impedance matching shifting) due to process, voltage, and temperature variations and modelling inaccuracy. A mm-wave amplifier with digitally controlled artificial dielectric transmission lines as fine frequency tuning components and an on-chip power detector as the frequency shifting detector has been implemented in 65 nm complementary metal-oxide-semiconductor to verify the effectiveness of the technique. The operating frequency of five amplifier chips is calibrated by running the self-healing algorithm on a field-programmable gate array development board. On average, the gain of the amplifier is improved by 2.60 dB from 13.66 to 16.26 dB and the input matching is improved by 12.78 dB from -4.89 to -17.67 dB at 56 GHz after the proposed self-healing procedure.

关键词： digitally controlled artificial dielectric transmission line on-chip power detector dielectric materials self-healing technique operation frequency shifting complementary metal-oxide-semiconductor gain 13.66 dB to 16.26 dB mm-wave amplifier frequency tuning component millimetre-wave amplifier impedance matching field-programmable gate array circuit tuning transmission lines size 65 nm digital control impedance matching shifting temperature variation gain 2.6 dB CMOS integrated circuits field programmable gate arrays frequency shifting detector frequency 56 GHz amplifier chip millimetre wave amplifiers

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FPGA Acceleration for 3-D Low-Dose Tomographic Reconstruction

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2021年第4期40卷 666-679页

作者： Zhang, Wentai Qiao, Linjun Hsu, William Cui, Yong Jiang, Ming Luo, Guojie Peking Univ Ctr Energy Efficient Comp & Applicat Beijing 100871 Peoples R China Peking Univ Sch Math Sci Dept Informat Sci Beijing 100871 Peoples R China Univ Calif Los Angeles Dept Radiol Sci Los Angeles CA 90095 USA Peking Univ Canc Hosp & Inst Minist Educ Dept Radiol Key Lab Carcinogenesis & Translat Res Beijing 100142 Peoples R China

X-ray computed tomography (CT) is commonly used to obtain vivo images to characterize diseases but results in radiation exposure to patients. Low-dose CT (LDCT) provides CT images of clinical quality with reduced cumulative radiation dose. Iterative image reconstruction methods with effective regularization are used for LDCT but generally require more computing resources and induce higher computational load than the conventional filtered backprojection (FBP) methods. The high computational demand of the iterative reconstruction (IR) with notably increased reconstruction time precludes its routine clinical application. In this work, we focus on the FPGA acceleration of a compute-intensive full IR (full-IR) algorithm based on the Mumford-Shah regularization. At the algorithmic level, we propose a beam-based asynchronous update algorithm to reduce the computational cost and alleviate the conflicts. At the hardware-level, we first present pipeline-friendly optimization for the original algorithm to increase the computation throughput. We then apply the LDCT-specific tiling strategy to improve the data reuse rate. The experimental results show that our implementation takes 8.5 min to reconstruct a typical physical phantom with the image quality comparable with the vendor's result. The FPGA implementation achieves 11.6x throughput against the state-of-the-art GPU version.

关键词： Asynchronous parallelism field-programmable gate array iterative image reconstruction low-dose computed tomography (CT)

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High-performance implementation of in-network traffic pacing for small-buffer networks

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COMPUTER COMMUNICATIONS 2013年第13期36卷 1450-1459页

作者： Hanay, Y. Sinan Dwaraki, Abhishek Hu, Kekai Wolf, Tilman NICT Ctr Informat & Neural Networks Osaka Japan Osaka Univ Adv Network Architecture Res Lab Osaka Japan Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

Demands on data communication networks continue to drive the need for increasingly faster link speeds. Optical packet switching networks promise to provide data rates that are sufficiently high to satisfy the needs of the future Internet core network. However, a key technological problem with optical packet switching is the very small size of packet buffers that can be implemented in the optical domain. Existing protocols, for example the widely used Transmission Control Protocol (TCP), do not perform well in such small-buffer networks. To address this problem, we have proposed techniques for actively pacing traffic at edge networks to ensure that traffic bursts are reduced or eliminated and thus do not cause packet losses in routers with small buffers. We have also shown that this traffic pacing can improve the performance of conventional networks that use small buffers (e.g., to reduce the cost of buffer memory on routers). A key challenge in this context is to develop systems that can perform such packet pacing efficiently and at high data rates. In this paper, we present the design and prototype of a hardware implementation of our packet pacing technique. We discuss and evaluate design trade-offs and present performance results from an prototype implementation based on a NetFPGA fieldprogrammable gate array system. Our results show that traffic pacing can be implemented with few hardware resources and without reducing system throughput. Therefore, we believe that traffic pacing can be deployed widely to improve the operation of current and future networks. (c) 2013 Elsevier B.V. All rights reserved.

关键词： Small-buffer network Traffic pacing Traffic burstiness field-programmable gate array Prototype

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MIPSfpga: using a commercial MIPS soft-core in computer architecture education

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IET CIRCUITS DEVICES & SYSTEMS 2017年第4期11卷 283-291页

作者： Harris, Sarah L. Harris, David M. Chaver, Daniel Owen, Robert Kakakhel, Zubair L. Sedano, Enrique Panchul, Yuri Ableidinger, Bruce Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89154 USA Harvey Mudd Coll Dept Engn Claremont CA 91711 USA Univ Complutense Madrid Dept Comp Architecture & Automat Madrid Spain Imaginat Technol Ltd Kings Langley WD4 8LZ Herts England

In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware-software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

关键词： field programmable gate arrays microprocessor chips computer science education computer architecture learning (artificial intelligence) source code (software) system-on-chip hardware-software codesign electronic engineering education MIPSfpga commercial MIPS soft-core processor computer architecture education learning materials teaching infrastructure nonobfuscated RTL source code MIPS microAptiv UP processor Imagination Technologies academic use field-programmable gate array hands-on learning system on chip SoC hardware-software codesign program debugging cache sizes content management policies CorExtend interface Linux

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Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

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PROCEEDINGS OF THE IEEE 2016年第10期104卷 1844-1863页

作者： Hanyu, Takahiro Endoh, Tetsuo Suzuki, Daisuke Koike, Hiroki Ma, Yitao Onizawa, Naoya Natsui, Masanori Ikeda, Shoji Ohno, Hideo Tohoku Univ Elect Commun Res Inst Sendai Miyagi 9807577 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9800845 Japan Tohoku Univ Grad Sch Engn Sendai Miyagi 9808579 Japan Tohoku Univ Frontier Res Inst Interdisciplinary Sci Sendai Miyagi 9808578 Japan

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

关键词： field-programmable gate array image recognition logic-in-memory architecture magneto-resistive RAM microcontroller unit (MCU) MTJ device MTJ/MOS-hybrid circuit nonvolatile LSI power gating standby power ternary content-addressable memory

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