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Impact of Hf content on positive bias temperature instability reliability of HfSiON gate dielectrics

MICROELECTRONICS RELIABILITY 2010年第5期50卷 614-617页

作者： Chen, H. W. Liu, C. H. Natl Taiwan Normal Univ Dept Mechatron Technol Taipei 106 Taiwan Natl Taipei Univ Technol Inst Mechatron Eng Taipei 10608 Taiwan

Metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating HfSiON dielectrics with different compositions have been fabricated using atomic layer deposition (ALD) and their positive bias temperature instability (PBTI) reliability has also been investigated. The experimental results indicate that the oxide trapped charge (N-ot) dominates the PBTI degradation process, and after PBTI stress the increment of oxide trapped charges (Delta N-ot) is about 2-3 orders of magnitude greater than the generation of interface traps (Delta N-it). Moreover, higher Hf concentration results in more pre-existing traps but slower trap creation rate. The charge pumping technique has been utilized to characterize the interfacial parameters, Delta N-it, Delta N-ot, and Delta D-it (the generation of the density of interface trap per energy and area). (C) 2010 Elsevier Ltd. All rights reserved.

关键词： METAL oxide semiconductor field-effect transistors TEMPERATURE effect RELIABILITY (Engineering) HAFNIUM compounds gate array circuits DIELECTRICS MICROFABRICATION EPITAXY

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Multi-gate non-volatile memories with nanowires as charge storage material

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MICROELECTRONICS RELIABILITY 2010年第5期50卷 603-606页

作者： Tsui, Bing-Yue Wang, Pei-Yu Chen, Ting-Yeh Cheng, Jung-Chien Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 300 Taiwan

Multi-gate non-volatile memory (NVM) cell is a promising approach in the next generation. In this work, the performance of NVMs using nanocrystals (NCs) and nanowires (NWs) as charge trapping materials were evaluated by three-dimensional simulation. It is found that the NWs located at different positions have different charge injection speeds. And the NW density will strongly affect the charge injection efficiency. The NW at channel center can result in large memory window and acceptable channel controllability. Although the total charges injected into NWs is lower than that injected into NCs under the same programming condition, using NWs as charge trapping material exhibits larger memory window and better channel controllability. It is suggested that the NW is a better choice than NC to be charge storage material from the perspective of memory performance. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： gate array circuits COMPUTER storage devices NANOWIRES ELECTRIC charge & distribution SIMULATION methods & models COMPUTER programming MICROELECTRONICS

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Improvement in RF performance of 40-nm InAs-channel based HEMTs using Pt gate sinking with two-step recess processes technology

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MICROELECTRONIC ENGINEERING 2010年第12期87卷 2625-2628页

作者： Kuo, Chien-I Hsu, Heng-Tung Wu, Chien-Ying Chang, Edward Y. Chen, Yu-Lin Lim, Wee-Chin Natl Chiao Tung Univ Dept Mat Sci & Engn Hsinchu 300 Taiwan Yuan Ze Univ Dept Commun Engn Chunli 320 Taiwan Yuan Ze Univ Commun Res Ctr Chunli 320 Taiwan

Forty-nanometer lnAs HEMT devices fabricated by two-step recess and Pt-buried gate were demonstrated for low-noise and low-power millimeter wave applications. The device exhibited a high transconductance of 1650 mS/mm at a drain voltage of 0.5 V. Improvement of the current-gain cutoff frequency from 395 GHz to 423 GHz was achieved with minimum noise figure below 2.5 dB up to 64 GHz at only 4.33 mW DC power consumption level. Besides, the output conductance was decreased from 2400 mS/ mm to 325 mS/mm. These superior performances are attributed to mitigation of the short-channel effect through the proposed technology. (C) 2010 Elsevier B.V. All rights reserved.

关键词： RADIO frequency PERFORMANCE evaluation INDIUM arsenide ELECTRON mobility FIELD-effect transistors gate array circuits NANOSTRUCTURED materials MICROFABRICATION ELECTRIC waves

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On the importance of the V_***-V_th parameter on LTPS TFT stressing behavior

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MICROELECTRONICS RELIABILITY 2010年第2期50卷 190-194页

作者： Moschou, Despina C. Kontogiannopoulos, Giannis P. Kouvatsos, Dimitrios N. Voutsas, Apostolos T. NCSR Demokritos Inst Microelect Aghia Paraskevi 15310 Greece Sharp Labs America Mat & Device Applicat Lab Camas WA 98607 USA

In this work we point out the importance of the device parameter ***-V-th (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters (V-th, G(***), S) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar G(***) degradation, as well as similar ***-V-th evolution. Therefore, G(***) evolution with stress time was found to be related more strongly to tail state generation, probed through ***-V-th, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant G(***) reduction could only be probed through the observation of a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense G(***) degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by ***-V-th evolution with stress. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： gate array circuits ELECTRIC conductivity EXTRAPOLATION LOW temperatures THIN film transistors STRAINS & stresses (Mechanics) ELECTRIC potential

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Circular DNA Logic gates with Strand Displacement

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LANGMUIR 2010年第3期26卷 1416-1419页

作者： Zhang, Cheng Yang, Jing Xu, Jin Peking Univ Minist Educ Key Lab High Confidence Software Technol Inst SoftwareSch Elect Engn & Comp Sci Beijing 100871 Peoples R China

Circular DNA logic gates were constructed on the basis of DNA three-way branch migration. In this logic system, circular DNA was used as a basic work unit and linear single-strand DNA was used as input and output signals. Making use of the circular structure, most of the DNA-specific recognition regions were designed in a single DNA ring. Depending on accurate DNA sequence recognition and highly effective strand displacement, the logic gates yielded correct results. fit addition, the positions of gold nanoparticles (AuNPs) were detected as an alternative approach to determine logic results. Thus, the accurate and tunable control of DNA/AuNPs may be applied widely ill DNA nanotechnology.

关键词： CIRCULAR DNA gate array circuits SIGNAL processing MOLECULAR recognition NUCLEOTIDE sequence COLLOIDAL gold NANOTECHNOLOGY

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Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation

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MICROELECTRONICS RELIABILITY 2010年第5期50卷 704-708页

作者： Wu, Chun-Yu Liao, Ta-Chuan Yu, Ming-H Chen, Sheng-Kai Tsai, Chung-Min Cheng, Huang-Chung Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 30039 Taiwan Nation Tsing Hua Univ Dept Mat Sci & Engn Hsinchu Taiwan

A novel omega-shaped-gated (Omega-gate) poly-Si thin-film-transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Omega-gate structure inherently covered two sharp corners manufactured simply via a side-wall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Omega-gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Omega-gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Omega-gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： gate array circuits THIN film transistors COMPUTER storage devices MICROFABRICATION TUNNELING (Physics) ELECTRIC fields PERFORMANCE evaluation

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Statistical variability in FinFET devices with intrinsic parameter fluctuations

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MICROELECTRONICS RELIABILITY 2010年第5期50卷 635-638页

作者： Hwang, Chih-Hong Li, Yiming Han, Ming-Hung Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chiao Tung Univ Inst Commun Engn Hsinchu 300 Taiwan Natl Nano Device Labs Hsinchu 300 Taiwan

High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively estimates the influences of the intrinsic parameter fluctuations on nanoscale fin-type field-effect-transistors and circuits by using an experimentally validated three-dimensional device and coupled device-circuit simulations. The dominance fluctuation source in threshold voltage, gate capacitance, cut-off frequency, delay time, and power has been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics: however, can be ignored in AC characteristics due to the screening effect of the inversion layer. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： ANALYSIS of variance FIELD-effect transistors FLUCTUATIONS (Physics) gate array circuits SIMULATION methods & models CHARGE coupled devices ELECTRIC capacity

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Field-Programmable gate array-based fluxgate magnetometer with digital integration

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JOURNAL OF APPLIED PHYSICS 2010年第9期107卷 09E714-1-09E714-3页

作者： Butta, Mattia Janosek, Michal Ripka, Pavel Czech Tech Univ Dept Measurement Fac Elect Engn Prague 16627 Czech Republic

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3360773]

关键词： FIELD programmable gate arrays FLUXgate magnetometers MAGNETOMETERS gate array circuits MAGNETIC devices

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Systematic study of the effect of La₂O₃ incorporation on the flatband voltage and Si band bending in the TiN/HfO₂/SiO₂/p-Si stack

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JOURNAL OF APPLIED PHYSICS 2010年第11期108卷 114107-114107页

作者： Di, Ming Bersch, Eric Clark, Robert D. Consiglio, Steven Leusink, Gert J. Diebold, Alain C. SUNY Albany CNSE Albany NY 12203 USA America LLC TEL Technol Ctr Albany NY 12203 USA

Recent studies have shown that La2O3 films can be used to adjust the threshold voltage (V-t) of NMOS Hf-based high-k/metal gate devices to desirable values, and a dipole at the high-k/SiO2 interface has been proposed to explain the V-t shifts. In order to investigate the mechanism of the V-t shift further, we have measured the flatband voltage (V-fb) and Si band bending of technologically relevant TiN/HfO2/La2O3/SiO2/p-Si stacks where the thickness and position of the La2O3 layer have been systematically varied. We observed systematic changes in V-fb, Si band bending and the HfO2-Si valence band offset as a function of La2O3 layer thickness and position. These changes can be explained by a band alignment model that includes a dipole at the high-k/SiO2 interface, thus supporting the work of previous authors. In addition, we have derived the theoretical relationship between V-fb and Si band bending, which agrees well with our experimental measurements. (c) 2010 American Institute of Physics. [doi:10.1063/1.3516483]

关键词： METAL oxide semiconductors THIN films gate array circuits SEMICONDUCTORS TRANSISTORS

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Image processing with cellular nonlinear networks implemented on field-programmable gate arrays for real-time applications in nuclear fusion

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REVIEW OF SCIENTIFIC INSTRUMENTS 2010年第8期81卷 083505-083505页

作者： Palazzo, S. Murari, A. Vagliasindi, G. Arena, P. Mazon, D. De Maack, A. Univ Catania Dipartimento Ingn Elettr Elettron & Sistemi I-95125 Catania Italy EURATOM ENEA Fus Consorzio RFX Assoc I-35127 Padua Italy CEA Cadarache Assoc EURATOM CEA F-13108 St Paul Les Durance France ENSAM Arts & Met Paris Tech Engn Coll F-13100 Paris Aix En Provence France JET EFDA Culham Sci Ctr Abingdon OX14 3DB Oxon England

In the past years cameras have become increasingly common tools in scientific applications. They are now quite systematically used in magnetic confinement fusion, to the point that infrared imaging is starting to be used systematically for real-time machine protection in major devices. However, in order to guarantee that the control system can always react rapidly in case of critical situations, the time required for the processing of the images must be as predictable as possible. The approach described in this paper combines the new computational paradigm of cellular nonlinear networks (CNNs) with field-programmable gate arrays and has been tested in an application for the detection of hot spots on the plasma facing components in JET. The developed system is able to perform real-time hot spot recognition, by processing the image stream captured by JET wide angle infrared camera, with the guarantee that computational time is constant and deterministic. The statistical results obtained from a quite extensive set of examples show that this solution approximates very well an ad hoc serial software algorithm, with no false or missed alarms and an almost perfect overlapping of alarm intervals. The computational time can be reduced to a millisecond time scale for 8 bit 496 x 560-sized images. Moreover, in our implementation, the computational time, besides being deterministic, is practically independent of the number of iterations performed by the CNN-unlike software CNN implementations. (C) 2010 American Institute of Physics. [doi:10.1063/1.3477994]

关键词： CAMERAS INFRARED imaging FUSION (Phase transformation) COMPUTER software industry gate array circuits

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