检索结果-内蒙古大学图书馆

Future IC fabrication rests on solutions to circuit and device scaling issues

SOLID STATE TECHNOLOGY 2002年第7期45卷 71-+页

作者： Zeitzoff, PM Murto, RW Huff, HR Int SEMATECH Inc Austin TX 78741 USA Princeton Univ Princeton NJ 08544 USA So Methodist Univ Dallas TX 75275 USA MIT Cambridge MA 02139 USA

The main scaling goal for high-performance logic is to maximize speed;for low-power logic, it is to maintain low leakage. currents. A key issue with scaling, is excessive gate leakage current. The introduction of high-k gate dielectric is expected to be driven by meeting the gate leakage current requirements of low-power logic in 2005 while implementation of high-k gate dielectric for high-performance logic is expected to follow shortly. Especially for 2007 and beyond, innovative solutions such as-enhanced mobility channels and nonclassical CMOS structures may be used, as well as elevated source-drain and associated advanced source-drain fabrication techniques.

关键词： gate array circuits DIELECTRICS SEMICONDUCTORS LOGIC circuits

来源：评论

学校读者我要写书评

暂无评论

DC pulse hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs

引用

IEEE TRANSACTIONS ON ELECTRON DEVICES 2001年第12期48卷 2746-2753页

作者： Chen, JH Wong, SC Wang, YH Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Taiwan Semicond Mfg Co Hsinchu 300 Taiwan

The dc pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate de pulse stress parameters in GIDL which include frequency, rise/fall time, and amplitude of stressing pulse. The contribution of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for de pulse hot-carrier-stress reliability analysis under circuit operation.

关键词： HOT carriers gate array circuits SCIENTIFIC experimentation

来源：评论

学校读者我要写书评

暂无评论

High-κ gate dielectrics:: Current status and materials properties considerations

引用

JOURNAL OF APPLIED PHYSICS 2001年第10期89卷 5243-5275页

作者： Wilk, GD Wallace, RM Anthony, JM Agere Syst Elect Device Res Lab Murray Hill NJ 07974 USA Univ N Texas Dept Mat Sci Denton TX 76203 USA Univ S Florida Ctr Microelect Res Tampa FL 33620 USA Bell Labs Lucent Technol Murray Hill NJ 07974 USA

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 mum complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-kappa materials by serving as an interfacial high-kappa layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation. (C) 2001 American Institute of Physics.

关键词： SILICA gate array circuits COMPLEMENTARY metal oxide semiconductors DIELECTRICS

来源：评论

学校读者我要写书评

暂无评论

Anomalous low-voltage tunneling current characteristics of ultrathin gate oxide (∼2 nm) after high-field stress

引用

JOURNAL OF APPLIED PHYSICS 2001年第10期89卷 5497-5501页

作者： Huang, CH Hwu, JG Natl Taiwan Univ Dept Elect Engn Taipei Taiwan

The effect of oxide barrier shape change caused by stress-induced interface trap charges on the low-voltage tunneling current (LVTC) characteristics of ultrathin gate oxide (similar to2 nm) is studied in this work. It was found that for an ultrathin gate oxide working in the direct tunneling regime, the LVTC behavior is strongly dependent on the barrier shape of the oxide. After high-field stress, anomalous LVTC phenomenon is observed. There is an invariant point existing in current-voltage curves. For a bias smaller than the value of the invariant point, the gate current decreases with stress time. However, for a bias larger than that, the gate current increases with stress time and then saturates. This phenomenon cannot be explained by conventional trap-assisted tunneling conduction, but by the change of tunneling probability due to barrier shape variation. An interface trap charge model is proposed to explain the observed invariant point mentioned above. From this, one can find the voltage corresponding to the midgap bias and, therefore, the initial effective oxide charge number density. (C) 2001 American Institute of Physics.

关键词： LOW voltage systems TUNNELING (Physics) OXIDES gate array circuits ELECTRONICS

来源：评论

学校读者我要写书评

暂无评论

Real-time video surveillance system using a field programmable gate array

引用

INTERNATIONAL JOURNAL OF IMAGING SYSTEMS AND TECHNOLOGY 2000年第2期11卷 130-137页

作者： Benkhalil, A Ipson, S Booth, W Univ Bradford Dept Elect & Elect Engn Bradford BD7 1DP W Yorkshire England

In this article, a stand-alone real-time video surveillance system Is presented. This system monitors a scene through a fixed master camera with a wide field of view and then directs a slave camera to capture automatically high-resolution images of moving targets within the scene. Motion detection is achieved by means of background differencing using adaptive thresholding and a temporal filter to continually update the background. The user can set the system to respond to different types of targets on the basis of their size and shape. The system utilizes a single-field programmable gate array to control the capture and storage of Image frames from the master camera, to perform all the necessary video-rate arithmetic and logical operations on images, and to generate all the signals needed to direct the slave camera. Results illustrating the highly successful operation of the system and comparisons with other reported surveillance systems are Included. (C) 2000 John Wiley & Sons, Inc.

关键词： ELECTRONIC surveillance FIELD programmable gate arrays REMOTE sensing SECURITY systems PROGRAMMABLE logic devices gate array circuits

来源：评论

学校读者我要写书评

暂无评论

Comparison of total dose effects on a voltage reference fabricated on bonded-wafer and polysilicon dielectric isolation

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2000年第6期47卷 2561-2567页

作者： Krieg, JF Neerman, CJ Savage, MW Titus, JL Emily, D Dunham, GW Van Vonno, N Swonger, J NAVSEA Surface Warfare Ctr Div Crane IN 47522 USA Intersil Corp Melbourne FL 32905 USA

Voltage reference devices, fabricated with two different starting materials, were used as a test vehicle to compare the total dose response of polysilicon dielectric-isolation (Poly-DI) and bonded-wafer version's ... 详细信息

关键词： gate array circuits BIPOLAR transistors DOSE-response relationship (Radiation)

来源：评论

学校读者我要写书评

暂无评论

Analysis of SEB and SEGR in super-junction MOSFETs

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2000年第6期47卷 2640-2647页

作者： Huang, S Amaratunga, GAJ Udrea, F Univ Cambridge Dept Engn Cambridge CB2 1PZ England

The electric field distribution in the super junction power MOSFET is analyzed using analytical modeling and numerical simulations in this paper. The single-event burn-out (SEB) and single-event gate rupture (SEGR) phenomena in this device are studied in detail. It is demonstrated that the super junction device is much less sensitive to SEE and SEGR compared to the standard power MOSFET. The physical mechanism is explained.

关键词： METAL oxide semiconductor field-effect transistors gate array circuits

来源：评论

学校读者我要写书评

暂无评论

IMPLEMENTATION OF AN ACTIVE-R FILTER BUILDING-BLOCK IN SEMICUSTOM VLSI

引用

INTERNATIONAL JOURNAL OF ELECTRONICS 1994年第3期76卷 469-482页

作者： SODERSTRAND, MA WATT, VHC GEE, KB MCGINTY, D HEWLETT PACKARD CORP COLORADO SPRINGS DIVCOLORADO SPRINGSCO 80907 HEWLETT PACKARD CORP SANTA ROSA DIVSANTA ROSACA 95406

A universal active-R building block was successfully designed and implemented using semi-custom VLSI (analogue gate-array) technology. The circuit makes use of the inherent charge storage in the low-frequency PNP transistors buffered by high-frequency NPN transistors which eliminates the need for capacitors and results in active-R filters that approximate the desired frequency response at high frequencies better than active-RC filters. A two-chip chip set is proposed for use as a practical building block for the p-plane design approach to active-R filters. The first chip contains two p-plane integrators which can be used to design any active-R filter. The second chip contains the parameter-compensation circuit which monitors the circuit on the first chip and uses this information to adjust the bias point on the integrator transistors in order to maintain constant integrator characteristics over a wide range of conditions including process variations, bias conditions, and temperature changes. As a result, the complete active-R filter maintains its characteristics better than active-RC filters over similar variations.

关键词： VERY large scale integration of circuits gate array circuits

来源：评论

学校读者我要写书评

暂无评论

DESIGN AND SIMULATION OF A HIGH-RELIABILITY NONVOLATILE CMOS EEPROM MEMORY CELL COMPATIBLE WITH SCALING-DOWN TRENDS

引用

INTERNATIONAL JOURNAL OF ELECTRONICS 1992年第1期72卷 73-87页

作者： ELHENNAWY, A King Abdul-Aziz University Jeddah P.O. Box 9028 Saudi Arabia

A simple but high-reliability non-volatile electrically-programmable and erasable memory cell (EEPROM) based on a non-avalanche injection mechanism is presented. This memory cell is composed of a double gate CMOS inverter. Circuit design allows fast programming and erasing (t(p) < 20 ms) with a single supply voltage of 5 V (at MOSFET channel length L = 2-mu-m and width = 20-mu-m). It employs a non-avalanche injection mechanism which guarantees a minimized oxide and interface degradation which leads to higher reliability and better operation stability. The EEPROM circuit latches the input data owing to the bidirectional hot carrier gate current. In this EEPROM, the majority of drawbacks of recent memories such as poor stability, long programming time, low reliability and the necessity of using two power supplies are removed. We then introduce a powerful simulation technique to compute V0(t), the output voltage, during programming and erasing cycles and also the programming time t(p). Computations have indicated good compatibility of the present EEPROM with the recent scaling-down trends in VLSI technology.

关键词： COMPUTER storage devices COMPUTER programming COMPLEMENTARY metal oxide semiconductors gate array circuits INTERFACE circuits

来源：评论

学校读者我要写书评

暂无评论

The development of a gate assisted turn-off thyristor for use in high frequency applications

引用

International Journal of Electronics 1974年第3期36卷 399-399页

作者： Raderecht, P.S [a] Westinghouse Brake and Signal Co. Ltd. Chippenham Wilts. England

The development of a high power, high frequency, inverter thyristor is described.
The techniques and procedures used to achieve forward blocking recovery times of less than 2 microseconds are summarized, and electrical test data are included to show that other thyristor parameters are not too adversely impaired.
This paper is concerned with the general problems involved in the design of high frequency thyristors, and briefly describes the techniques used to develop this particular device. [ABSTRACT FROM AUTHOR]

关键词： THYRISTORS MODULATORS (Electronics) gate array circuits

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：